1. Micro-Research Finland Oy Timing System Developments Jukka Pietarinen EPICS Collaboration Meeting Shanghai March 2008

2. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Register Map Changes (new register mapping) Now available for –CompactPCI boards –PMC-EVR Main features –Direct addressing of registers, sequencer memories, etc. –Register space has grown to 64 kbytes –One type of EVR pulse generator – 128 bit wide EVR event mapping RAM: No overlapping mapping bits –Mapping registers for HW inputs and outputs –EVG interrupt support –EVR Upstream signaling Will be available for VME versions later

3. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 EVR Pulse Generator One type of EVR pulse generator: –Registers for delay, width, prescaler with SW probable width –No more different types of outputs: PDP, OTP, TEV, LVL

4. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Event Mapping RAM Event codeInternal func.Pulse triggerPulse setPulse clear 132 bits 2 … 255 Map bitDefault event codeFunction 127n/aSave event in FIFO 126n/aLatch timestamp 125n/aLed event 124n/aForward event 1230x79Stop event FIFO 102 to 122n/a(Reserved) Map bitDefault event codeFunction 1010x7aHearbeat 1000x7bReset Prescalers 990x7dTimestamp reset event 980x7cTimestamp clock event 970x71Seconds shift register ‘1’ 960x70Seconds shift register ‘0’

5. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Register Map Changes Same set of VHDL sources for all form factors EVR configuration determined by a VHDL package –Number of front panel I/O –Number of Universal I/O modules –Backplane I/O –Number of pulse generators (max. 32) –Pulse delay and width extents

6. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 VHDL package for cPCI-EVR -- Event Receiver configuration parameters -- C_EVR_PULSE_GENS sets the number of internal pulse generators constant C_EVR_PULSE_GENS : integer := 10; constant C_EVR_TTL_INPUTS : integer := 2; -- C_EVR_TTL_OUTPUTS defines the number of front panel TTL outputs constant C_EVR_TTL_OUTPUTS : integer := 0; -- C_EVR_CML_OUTPUTS defines the number of front panel CML outputs -- note: the CML output mapping registers are appended after the -- TTL output mapping registers constant C_EVR_CML_OUTPUTS : integer := 0; -- C_EVR_UNIV_OUTPUTS defines the number of Universal outputs -- = twice the number of Universal I/O slots constant C_EVR_UNIV_OUTPUTS : integer := 10; constant C_EVR_UNIV_INPUTS : integer := 10; -- C_EVR_GPIOS defines the number of GP I/Os in Universal I/O slots constant C_EVR_GPIOS : integer := 8; -- C_EVR_TB_OUTPUTS defines the number of Transition Board/Rear I/O/ -- PXI star trigger/trigger bus outputs constant C_EVR_TB_OUTPUTS : integer := 0;

7. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 VHDL package for cPCI-EVR (cont.) -- C_EVR_PRESCALERS defines the number of prescalers constant C_EVR_PRESCALERS : integer := 3; constant C_EVR_PULSE_PRESC_RANGE : integer_array(0 to C_EVR_PULSE_GENS-1) := (16, 16, 16, 16, 0, 0, 0, 0, 0, 0); constant C_EVR_PULSE_DELAY_RANGE : integer_array(0 to C_EVR_PULSE_GENS-1) := (32, 32, 32, 32, 32, 32, 32, 32, 32, 32); constant C_EVR_PULSE_WIDTH_RANGE : integer_array(0 to C_EVR_PULSE_GENS-1) := (32, 32, 32, 32, 16, 16, 16, 16, 16, 16); constant C_EVR_PRESC_RANGE : integer_array(0 to C_EVR_PRESCALERS-1) := (16, 16, 16); constant C_EVR_MICREL_WORD : std_logic_vector := X"0C928166"; constant C_EVR_USEC_DIVIDER : std_logic_vector := X"007D"; constant C_EVR_USE_TRANSMITTER : boolean := TRUE; -- C_EVR_ENABLE_BACKWARD_CHANNEL enables EVR event transmission and -- disables loopback of received event stream constant C_EVR_ENABLE_BACKWARD_CHANNEL : boolean := TRUE;

8. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Downstream Timing Event Generator (EVG) 12-Way Fan-Out RF input (50 MHz to 1.6 GHz) Rep. Rate Trigger Input e.g. 50 Hz TTL Hardware Triggers/Clocks 12-Way Fan-Out Event Receiver (EVR) Hardware Outputs Event Receiver (EVR) Multimode fiber

9. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Timing System with Upstream Event Generator (EVG) Fan-Out/Concentrator RF input (50 MHz to 1.6 GHz) Rep. Rate Trigger Input e.g. 50 Hz TTL Hardware Triggers/Clocks Fan-Out/Concentrator Event Receiver (EVR) Hardware Outputs Event Receiver (EVR) Multimode fibers

10. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Timing System Upstream Channel Backward events –EVR send events on external HW triggers –Forwarding of received events filtered by event code –Concentrators forward events on first in first out basis Backward Distributed Bus –External inputs provide signals to up to eight backward distributed bus signals –Concentrators combine distributed buses from all EVRs (bitwise OR) Backward Data Transmission –Data buffers of up to 2k may be send upstream –Concentrators pass data on as-is, if EVR identification is needed and ID has to be included in data –Note: concentrator buffering capacity is limited Fiber delay measurement

11. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Fan-Out Concentrator Module (cPCI-FOUT-CT-8)

12. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Fiber Delay Measurement Setup EVG FOUT- CT-8 EVR Loopback EVR Loopback EVR Scope Fiber under test Fiber length Scope Delay Timing SystemDiff relative error mns mm 946,414340,418294,0040,000 24120,72414,733294,0130,0091,797 44219,641513,628293,987-0,017-3,393 84416,99711,010294,0200,0163,170 164812,6251106,629294,004-0,001-0,105 2941455,4461749,457294,0110,0071,340 5542741,6923035,692294,000-0,005-0,930

13. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Fiber Delay Measurement std.dev. between 10:40 and 10:55 2.2 ps Scope offHeater 50˚C Heater 70˚C Heater 80˚C

14. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Fiber Delay Measurement Cold Spray

15. Micro-Research Finland Oy jukka.pietarinen@mrf.fi12.3.2008 Form Factors Event Generator –VME64x –PXI/CompactPCI Event Receiver –VME64x –PMC –PXI/CompactPCI 3U –Future form factors: CompactPCI 6U? CompactRIO (National Instruments)? EPIC form factor? (see http://www.pc104.org) –Integrated CPU (either soft-CPU inside FPGA or Freescale Coldfire) –Integrated EVR –PC104 bus / PCI bus uTCA?