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Andrew Faulkner1 Technology Readiness Levels 4 th SKADS Workshop, Lisbon Technology Readiness Levels TRLs Andrew Faulkner.

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Presentation on theme: "Andrew Faulkner1 Technology Readiness Levels 4 th SKADS Workshop, Lisbon Technology Readiness Levels TRLs Andrew Faulkner."— Presentation transcript:

1 Andrew Faulkner1 Technology Readiness Levels 4 th SKADS Workshop, Lisbon Technology Readiness Levels TRLs Andrew Faulkner

2 Andrew Faulkner2 Technology Readiness Levels 4 th SKADS Workshop, Lisbon Purpose 1.To identify where we are in the long term development cycle of the SKA technology 2.To identify ‘missing’ development work 3.To convince ourselves and the international community that we are ‘on-track’

3 Andrew Faulkner3 Technology Readiness Levels 4 th SKADS Workshop, Lisbon Tech. Readiness LevelDescription 1. Basic principles observed and reported This is the lowest "level" of technology maturation. At this level, scientific research begins to be translated into applied research and development. 2. Technology concept and/or application formulated Once basic physical principles are observed, then at the next level of maturation, practical applications of those characteristics can be 'invented' or identified. At this level, the application is still speculative: there is not experimental proof or detailed analysis to support the conjecture. 3. Analytical and experimental critical function and/or characteristic proof of concept At this step in the maturation process, active research and development (R&D) is initiated. This must include both analytical studies to set the technology into an appropriate context and laboratory-based studies to physically validate that the analytical predictions are correct. These studies and experiments should constitute "proof-of-concept" validation of the applications/concepts formulated at TRL 2. 4. Component and/or breadboard validation in laboratory environment Following successful "proof-of-concept" work, basic technological elements must be integrated to establish that the "pieces" will work together to achieve concept-enabling levels of performance for a component and/or breadboard. This validation must be devised to support the concept that was formulated earlier, and should also be consistent with the requirements of potential system applications. The validation is relatively "low-fidelity" compared to the eventual system: it could be composed of ad hoc discrete components in a laboratory. 5. Component and/or breadboard validation in relevant environment At this level, the fidelity of the component and/or breadboard being tested has to increase significantly. The basic technological elements must be integrated with reasonably realistic supporting elements so that the total applications (component-level, sub- system level, or system-level) can be tested in a 'simulated' or somewhat realistic environment. 6. System/subsystem model or prototype demonstration in a relevant environment A major step in the level of fidelity of the technology demonstration follows the completion of TRL 5. At TRL 6, a representative model or prototype system or system - which would go well beyond ad hoc, 'patch-cord' or discrete component level breadboarding - would be tested in a relevant environment. At this level, if the only 'relevant environment' is the environment of space, then the model/prototype must be demonstrated in space. 7. System prototype demonstration in a real environment TRL 7 is a significant step beyond TRL 6, requiring an actual system prototype demonstration in a site environment. The prototype should be at a representative scale of the planned operational system and the demonstration must take place at a site with similar characteristics to the target site. 8. Actual system completed and 'qualified' through test and demonstration In almost all cases, this level is the end of true 'system development' for most technology elements. This might include integration of new technology into an existing system. 9. Actual system proven through successful actual operations In almost all cases, the end of last 'bug fixing' aspects of true 'system development'. This might include integration of new technology into an existing system. This TRL does not include planned product improvement of ongoing or reusable systems. NASA TRL definitions

4 Andrew Faulkner4 Technology Readiness Levels 4 th SKADS Workshop, Lisbon TRLs mapped to SKA timeline Ref: NASA http://en.wikipedia.org/wiki/Technology_Readiness_Level SKA in operation SKA Phase 1 Target for AAVP PrepSKA & SKADS SKADS Mostly pre-SKADS work Basic Technology Research Research to Prove Feasibility Technology Development Technology Demonstration System/Subsystem Development Full System Test & Operations

5 Andrew Faulkner5 Technology Readiness Levels 4 th SKADS Workshop, Lisbon Review undertaken

6 Andrew Faulkner6 Technology Readiness Levels 4 th SKADS Workshop, Lisbon TRL: 1 2 3 4 5 6 7 8 9 DS3-T1Phase Transfer: optical tx terminal equipment Analogue fibre data links COTS Data links Component data links: DFB laser based link subsystems Components for DFB laser subsystems 10 Gbps 1550 nm SMF subsystems Components for 10 Gbps 1550 nm SMF link DS3-T2Backend Processing Correlator Software architecture DS3-T3Design of SKACost tool and simulation Conceptual design of SKA Station level beamforming DS3 TRLs

7 Andrew Faulkner7 Technology Readiness Levels 4 th SKADS Workshop, Lisbon TRL: 1 2 3 4 5 6 7 8 9 DS4-T1LNA InP Si-Ge Si GaAs ADC InP Si DS4-T2Digitisation require’ts DS4-T3RFI algorithms: Excision Detection Spectral filtering Spatial filtering Single channel filtering DS4-T4Antenna: Vivaldi non-Vivaldi array configuration Differential LNA + matching DS4-T5Beamforming: Analogue Photonic Digital algorithms Digital hardware DS4-T6Mechanical Const’n: Array construction Cooling Electronics construction Material choice Analogue sig. cond. RFI Shielding Clock dist’n : Station level Board level

8 Andrew Faulkner8 Technology Readiness Levels 4 th SKADS Workshop, Lisbon TRL: 1 2 3 4 5 6 7 8 9 DS5-T1Array performance DS5-T2Low cost manufacturability Tile electronics Digital processing Array material choice DS6System Clock distribution DS5 & 6 TRLs

9 Andrew Faulkner9 Technology Readiness Levels 4 th SKADS Workshop, Lisbon Observations SKADS is where we would expect:TRL 3 – 6 The lowest TRLs typically require large implementations There will be some ‘normalising’ of the figures The relationship of today’s design and SKA is not clear enough But……..

10 Andrew Faulkner10 Technology Readiness Levels 4 th SKADS Workshop, Lisbon System related TRLs We need to know/show system parameters are met e.g.: System temperature Dynamic range performance Cost! Beam purity Polarisation AAs meet Power requirements etc This is tricky! Need to convert system level work into technical performance measures

11 Andrew Faulkner11 Technology Readiness Levels 4 th SKADS Workshop, Lisbon Over this final year of SKADS We will be refining the TRL of System and Components Please keep commenting …..


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