1. Xilinx Programmable Logic Design Solutions Version 2.1i Designing the Industry’s First 2 Million Gate FPGA Drop-In 64 Bit / 66 MHz PCI Design

2.  Industry’s fastest compilation times  Industry’s highest performance  Industry's best support for High-Level design flows —HDL design —Design re-use / Cores —Robust functional and timing verification —Internet enabled design  Support for the industry’s largest FPGAs  Products configured to meet your design needs State of the Art Programmable Logic Design

3. Density Leadership XC4085XLA Virtex V1000 75 million Transiistors Density (system gates) 10M Gates In 2002 Next Generation Virtex 2 Million System Gates Today! XC40250XV 10M 2M 1M 180k 500k 1997 1998 1999 2000 2001 2002

4. Internet Enabled Software 4Internet Team Design 42 Million Gate support 4100K Gates < 1 minute 4Embedded Core Generator 4Drop-In 64 bit / 66 MHz PCI Software Leadership 4Push Button Design 4Minimum Delay Reporting 4Voltage/Temperature Prorating 4Floorplanning 1998 1999 Ease Of Use v2.1i v1.5i

5. 2X 1X 3X 7X 4X 6X 5X 4.2X Benchmark Results Virtex vs. 10KE Compilation Time 9.3X ÝBenchmarks are comparing Virtex -6 with 10KE-1 using Alliance version 2.1i vs. MAX+PLUS2 9.1 ÝDesign suite consists of 22 HDL customer designs ranging from XCV50-XCV600 Xilinx 2.1i is FASTER Xilinx 2.1i is FASTER Non Timing Driven Timing Driven 3X 2X 4X 5X 1X 7X 6X

6. 20% 10% 30% 40% 0% 60% 50% 37% Virtex is FASTER Virtex is FASTER Non Timing DrivenTiming Driven 20% 10% 30% 40% 0% 60% 50% ÝBenchmarks are comparing Virtex -6 with 10KE-1 using Alliance version 2.1i vs. MAX+PLUS2 9.1 ÝDesign suite consists of 22 HDL customer designs ranging from XCV50-XCV600 Benchmark Results Virtex vs. 10KE Performance

7. Internet Team Design Solves 21st Century Design Challenges Design Team Leader Schematic Engineer VHDL Engineer Verilog Engineer Core Engineer The Problem  Million+ Gate Designs  Variety of Flows  Remote Location of Designers  Design Revision Management The Solution  Communication  Coordination  Integration

8. Internet Team Design Product Description A web-based facility to coordinate and manage team-based design projects Key features include:  Facilitates project schedule, assignments and communication among team members  Coordination of input source and netlist files from multiple designers  Provides access to implementation reports, timing simulation and configuration files

9. Synopsys FPGA Express TM 3.2 —Advanced synthesis delivers faster clock speeds, and more efficient utilization  Powerful HDL design: —TCL scripting enables ASIC - style design flow —Advanced Analysis features simplify design debugging: —Integrated Schematic Viewing and Static Timing Analysis (VISTA TM ) —Consistent signal naming  Push-Button HDL Performance:

10. The Real 64/66 PCI PCI64/66 Zero wait-state FIFO(s) User Design DMA(s) 64-bit Interface Real Performance  Compliant zero wait-state at 66MHz  Full 64-bit data path Real Compliance  PCI v2.2 Initiator and Target  Guaranteed timing Real Flexibility  Uses standard Virtex FPGA  Back-end de-coupled from core 64-bit, 66MHz PCI

11. Xilinx Alliance Series Programmable Logic Design Tools Integrated Into Your EDA Environment  Robust support for the complexities of multi-million gate FPGA design —High performance synthesis —Advanced design analysis through board level verification –STAMP and LMG models  Industry’s first Internet Team Design methodology  Productivity enhancements speed system level design —Dramatic compile time improvements —Extensive IP —Design timing and layout analysis tools

12. Xilinx Foundation Series A Complete, Ready to Use Programmable Logic Design Environment  Easy to use, mixed-level design environment —Industry's fastest compilation times —Embedded core generation tool —Industry’s most comprehensive on-line support  Powerful, mixed-language synthesis from Synopsys R  Drop-In PCI design —64 bit / 66 MHz Virtex “Real PCI” —32 bit / 33 MHz SpartanXL PCI