1. 40551 Logic Synthesis Optimization Dr. Yaser M. Agami Khalifa Fall 2004 Lecture # 1

2. Contact Information Dr. Yaser M. A. Khalifa Location: REH 202 Office Hours: MW 2:00 – 4:00 PM Phone: (845) 257-3764 FAX: (845) 257-3730 E-mail: yaserma@engr.newpaltz.edu Website: www.engr.newpaltz.edu/~khalify

3. Course Description The aim of this course is to present automatic logic synthesis techniques for computer-aided design (CAD) of very large-scale integrated (VLSI) circuits and systems. This course will broadly survey the state of the art, and give a detailed study of various problems, pertaining to the logic-level synthesis of VLSI circuits and systems, including: two-level Boolean network optimization, multi-level Boolean network optimization, technology mapping for library-based designs and field- programmable gate-array (FPGA) designs, and state-assignment and re-timing for sequential circuits. The course will also cover various representations of Boolean functions, such as binary decision diagrams (BDDs), and discuss their applications in logic synthesis

4. Course Objectives To introduce students to basic optimization techniques used in circuits design To introduce students to advanced tools and techniques in digital systems design. These include Hardware Modeling and Compilation Techniques. To introduce in details Logic-Level synthesis and optimization techniques for combinational and sequential circuits. To introduce students to Library binding algorithms to achieve implementations with specific cell libraries.

5. Textbook De Micheli G.: “Synthesis and Optimization of Digital Circuits”, McGraw Hill, 1994.

6. Course Contents [1] Introduction a) Semiconductor Technologies and Circuit Taxonomy b) Design of Microelectronic Circuits c) Computer-Aided Synthesis and Optimization [2] Optimization Algorithms a) Graph Theory b) Combinatorial Optimization c) Fundamental Algorithms d) Graph Optimization Algorithms e) Boolean Algebra and Applications

7. Course Contents [3] Hardware Modeling a) Hardware Modeling languages b) Abstract Models c) Compilation and Behavioral Optimization [4] Architecture Synthesis a) Circuit Specifications for Architectural Synthesis b) Fundamental Architectural Synthesis Problems c) Area and Performance Estimations

8. Course Contents [5] Two-Level Combinational Logic optimization a) Logic Optimization Principles b) Operations on Two-Level Logic Covers c) Algorithms for Logic Minimization d) Symbolic Minimization and Encoding Problems e) Minimization of Boolean Relations. [6] Multi-Level Combinational Logic Optimization a) Models and Transformations for Combinational Networks b) The Algebraic Model c) The Boolean Model d) Algorithms for Delay Evaluation and Optimization e) Rule-based Systems for Logic Optimization

9. Course Contents [7] Sequential Logic Optimization a) Sequential Circuit optimization Using State-Based Models b) Sequential Circuit optimization Using Network Models c) Implicit Finite-Stet Machine Traversal Methods d) Testability Considerations for Synchronous Circuits [8] Cell-Library Binding a) Problem Formulation and Analysis b) Algorithms for Library Binding c) Specific problems and Algorithms for Library Binding d) Rule-Based Library Binding

10. Course Contents [9] State of the Art and Future Trends

11. Homework Approximately ten written homework assignments will be given throughout the semester related to the concepts covered during the lectures. Each assignment must be turned in by the end of class on the scheduled due date.

12. Homework Submission of late work will be accepted by the professor; however the maximum possible score will be scaled by the percentage shown in the following table. Homework in due time 100.0% One day late 75.0% Two days late 50.0% > Two days 0.0% Special circumstances will be considered provided the professor is contacted before the due date.

13. Quizzes! Unannounced short (drop) quizzes may be given during the class period from time to time. They may cover previous work or lectures.

14. Course Assessment Project10 % Homework Assignments 20 % Research Paper10 % Quizzes10 % Midterm Exams20 % Final Exam30 %

15. Exam Dates Midterm Exams Wednesdays, October 13 th, and November 17 th Final ExamTBA

16. Grading Policy A > 90 % B80 % - 90 % C70 % - 80 % F< 70 %