1. Low Voltage Low Power constant - g m Rail to Rail CMOS Op-Amp with Overlapped Transition Regions ECEN 5007 9/3/02 Vishwas Ganesan

2. Motivation Low Supply Voltage Operation Constant g m Low power consumption making it suitable for portable applications. Reduced chip area.

3. Why this paper came up ? Complementary differential pairs operate in parallel. This leads to one pair turned on and one off when input is near rails and both pairs on at the middle of the input range leading to gm being twice the value than the former case

4. Other Circuit Proposals 1. Variation in the tail current in the differential paper doubling gm when only one pair is active. 2. Comparing currents from p and n differential pairs and the maximum current between them is selected and processed for gm constant by maximum-selecting circuitry. 3. Current bleed circuits 4. Square root circuit

5. Difficulties with other circuits Increase in slew rate due to increase in tail current. Extra circuitry – Signal processing circuits and many more current mirrors. All this leads to complication, Power consumption and more die.

6. Complementary Input Stage Gm is constant if √ (β n I sn) + √ (β p I sp) = constant Cutoff : Isn = 0 Vss ≤ Vcm ≤ Vn - Transition Isn = Isn ( Vcm ) Vn - < Vcm ≤ Vn + Saturation Isn = ß MBn ( V GMBn – V ss – V t n ) 2 V n + < V cm ≤ V dd

7. General Transition graph This shows the transition region overlap of a general n-p differential pair.

8. Design

10. Complementary Input Stage with DC Level Shifter Use a dc level shifter to shift the p-transition curve leftward to overlap the n-transition curve. Vshift small  gm exceeds normal limit Vshift large  gm drops below limit ∆ Voptimal yields constant Gm 2V GMBN <∆Voptimal< 2V GMBN + √(I sno /β M1 )

11. Plot Of g m vs Vcm

12. OPAMP Circuit

13. OPAMP Implementation DC level shifters implemented by 2 pairs of PMOS source followers MS1-MS4 Three stages 1. Complementary input stage 2. Folded cascoded stage M21-M28 provides high gain 3. Class AB output stage M30-M33 4. MB1 and MB11 are biasing transistors.

14. Frequency Response Amplitudes and phase plots show unstability due to varying gm.

15. My simulation results Input offset voltage30 mV Power dissipation.36 mW Output Voltage swing1.1 V to -1V

16. Simulation plots

17. Paper Results Input offset voltage3 mV Power dissipation.31 mW OpAmp area.12 mm 2 Output Voltage swingVss + 0.04 to Vdd – 0.07 V

18. Conclusions DC level shifters can be used to overlap transition regions to obtain constant gm. Low Power dissipation was achieved Low supply voltages. There is considerable gain achieved leading to CMRR improvement.