1. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney1 ME/DPU OBSW Presentation ME presentation (both DPU and OBSW) Management of the SW (documentation, team, responsabilities...) Requirements of the specific subsystem (User Requirements, Functional Requirtements, Architectural Design) Design & production of the Code Testing & Delivery

2. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney2 ME/DPU Localisation Ariane5 + Herschel- Planck Planck S/C Planck SVM HFI ME/DPU Prime and Redundant

3. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney3 CQM ME/DPU

4. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney4 CQM DPU-MP

5. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney5 CQM DPU-PDP

6. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney6 CQM1 DPU-DP

7. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney7 OBSW Interfaces

8. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney8 OBSW parts OBSW contains 4 parts: –Several test routines (TSW) Used for DPU H/W validation A sub-set used by BSW for DPU H/W check –One boot software (BSW) Starting after : –28V switch Off/On –watch-dog reset –S/W reset –Several drivers (DSW) Used by TSW, BSW ASW to control Mil-Std-1553B, HSL, LSL, HSK scan, LOBT, SRAM Parity, Relay, Wachdog, EEPROM. –One application software (ASW). ASW + DSW developped under VspWorks RTK BSW + TSW developped without VspWorks RTK

9. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney9 ME OBSW Documentation

10. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney10 DPU OBSW Team DSW+TSW+BSW development & test: M. Dehamme ASW development & test:J. Lebahar EUS development & test:J.C. Marrucho OBSW manager:J.L. Béney Configuration Manager:B. Mansoux OBSW PA Manager:B. Mansoux

11. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney11 ME OBSW Requirements 1/2 First level of requirements in the Annoucement of Opportunity (AO). An URD has been written to make an assessment of the AO and to complete the requirements (with requirement numbering). With Archeops experience return, requirements has been refined and sometimes changed particularly on science data treatment !!!! ME OBSW interfaces has slightly changed (S/C & REU)

12. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney12 ME OBSW Requirements 2/2 A major requirement listed in the AO: Maintain the observation continuity. It can be partitionned in 2 second order requirements: –HFI needs to recover autonomously any untimely FPU warm-up => FDIR study. –HFI needs of re-synchronisation features more than re- configuration features (i.e. if a sub-system failed, ME OBSW shall restart the sub-system in its previous state without re- setting other HFI parts => FDIR and Re-synchronisation study. All these requirements change will be updated in the ME OBSW technical specifications document (Not in the URD).

13. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney13 ME OBSW functions –OSF1: Monitoring and commanding the HFI –OSF2: Telecommands management –OSF3: Cooler data acquisition –OSF4: Readout data acquisition –OSF5: DPU-PSU housekeeping data acquisition –OSF6: Housekeeping telemetry packets formatting and sending –OSF7: Science data compression –OSF8: Science telemetry packets formatting and sending –OSF9: Software maintenance –OSF10: Boot and diagnostic software.

14. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney14 I/F with Ground and S/C

15. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney15 OSF2: Telecommand Packet

16. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney16 TC Acknowledge

17. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney17 OSF1: Mode Management

18. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney18 OSF1: FDIR Mode FDIR Mode Isolation and Recovery Mode transition DPU mode resynchronisation REU or 4KCDE mode resynchronisation ManualOnly by TC DPU automaticOnly by TCAutomatic if specifiedAutomaticOnly by TC HFI automaticAutomaticAutomatic if specifiedAutomatic

19. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney19 OSF1: Identified FDIR SystemFailureDetectionIsolationS/S involved RecoveryS/S involved REU beltShort-circuit on DC-DC converter primary side LCL fall downBy PDP relay MELCL switch onS/C REUResynchronisation failureFlag REUNone-Belt detection procedure ME S/C DPU proc Lost of communicationNo or bad TM packet None-LCL switch off- on ME S/C REU proc Lost of communicationNo or bad data packet None-LCL switch off- on ME S/C DCELost of communicationNo or bad data packet None-LCL switch off- on ME S/C 4KCDE proc Lost of communicationNo or bad data packet None-LCL switch off- on ME S/C SystemFailureDetectionIsolationS/S involvedRecoveryS/S involvedStatus DCEBlockageOn pressure and flowNone-Local bakingME, DCETBD 4KCDEBlockageOn pressure and flowNone-Local bakingME, 4KCDETBD

20. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney20 OSF1: FDIR example FDIR example in discussion with Alcatel

21. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney21 Telemetry Packets 1/2

22. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney22 Telemetry Packets 2/2 OSF6: Housekeeping and diagnostic telemetry –Around 1300 Telemetry Parameters downloaded by service 3 –Around 1300 Command Parameters –DataRate close to 3,7 kbit/s with 10% margin OSF8: Science telemetry –In the previous table, * means that raw data are coded on 2 x (16 samples (on 16 bits) per half period)

23. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney23 ASW Time-tagging

24. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney24 ASW Task communication

25. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney25 ASW Task triggering

26. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney26 ASW Load

27. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney27 BSW architecture

28. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney28 OBSW Development environment –EZ tools (Analog Devices) at processor level (through JTAG) –Virtuoso gives standard tools of a Multi-task OS (task, semaphore, etc..) –Virtuoso Monitoring tools (Eonic) at RTK level: (Communication with BSP through RS232) –Development of ASW on 21060 target with partial simulation of Hardware.

29. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney29 ASW design & production 1/2 Function\VersionV1V2V3 OSF1: Mode managementBasicCompleteYes OSF1: Telecommand Transmission TC-TM(8,x)BasicComplete OSF1: HP-PSICD Packet Transmission Control service: TC-TM(14,x)No Yes OSF1: HP-PSICD Test service: TC(17,x)No Yes OSF1: HP-PSICD Event service: TM(5,x)NoPartialComplete OSF1: FDIR managementNo Yes OSF1: TC filteringNo Yes OSF1: Re-synchronisation managementNo Yes OSF2: Telecommands management: TC-TM(1,x)PartialComplete OSF3: Cooler data acquisitionPartialComplete OSF4: Readout data acquisitionComplete OSF5: DPU-PSU housekeeping data acquisitionComplete OSF6: Housekeeping telemetry packets formatting and sending : TC-TM(3,x)Complete OSF7: Science data compressionPartialComplete OSF8: Science telemetry packets formatting and sending: TM(21,x)NoComplete OSF8: Science telemetry datarate managementNo Complete OSF9: Software maintenance: TC-TM(6,x)NoComplete

30. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney30 ASW design & production 2/2 ASW Architectural Design has been done. No detailed design is foreseen since the AD is almost a DD. Coding phase has begun with: –Version 1 developped on 21060 target (ATLAS) and ported on 21020 target (Breadboard Model) –Version 2: current version in developpement on BM to allow the Interface Tests and the Calibration Tests –Version 3: Last version integrated on the CQM and delivered for AIT-AIV warm unit tests. –Version 3 release ? will be provided with the PFM/FS after having performed the complete test sequence. Version3 will integrate the OBSW high level features.

31. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney31 BSW Design & Production Most of BSW parts are already developped and are used by TSW and ASW. The detailed design has begun and is an assembly of these parts. 2 versions are foreseen: –V1 will be delivered with the Breadboard Model for calibration test –V2 will be delivered with the CQM for warm unit test. –V2 release ? will be delivered with PFM and FS.

32. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney32 ME OBSW Test Activity 1/2 Critical parts of the ME OBSW are identified: –BSW with Memory check, 1553 I/F check TSW 1553 I/F DSW (Data Link Layer & Transfert Layer) HP-PSICD services used in BSW (1, 3, 6, 8) ASW Loader But critical and no-critical parts will be tested at: –Unit Test level –Integration Test level –Qualification Test level –Acceptance Test level Only testing coverage will be different between critical and no-critical parts.

33. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney33 ME OBSW Test Activity 2/2 Qualification and acceptance testing activity will be performed by OBSW part developpers before CQM delivery. Unit and Integration testing activity will be performed later before PFM delivery. Depending of the OBSW part, they could be sub-contracted. Test Requirements, Plans and Report will be used to trace the testing activity according to the template of the next slide. They will be prepared in a first time for Qualification and Acceptance tests.

34. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney34 OBSW Test RPR 1/2

35. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney35 ME OBSW Test RPR 2/2

36. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney36 Test environment at S/S level

37. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney37 End of presentation. Thank you.

38. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney38 Software quality Software management plan –Responsabilities –Development tools description –Configuration management tools description –Software development plan Description of the life cycle (almost a V cycle) Description of foreseen review –Software validation and verification plan overview Software validation and verification plan –Test (Requirement, Plan and Report) –Test level (Unit, Integration, Qualification and Acceptance) –Test coverage

39. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney39 Présentation du DPU/DP Processeur : TSC21020x Program Memory : –PROM : 32k x 48 bits –EEPROM : 128k x 48 bits –SRAM : 128k x 48 bits Data Memory : –SRAM : 128k x 32 bits SEU detection Latch-up protection LOBT (48 bits counter) I/F MIL-STD-1553B I/F HSL and I/F LSL DPU HSK acquisition –6 temperatures, 9 powers.

40. HFI Software Internal Review PLANCK 10 July 2003J.L. Béney40 Carte Proto DPU-DP (BM)