1. MARS A Scan-Island Based Design Enabling Pre-Bond Testability in Die-Stacked Microprocessors Dean L. Lewis Hsien-Hsin S. Lee Georgia Institute of Technology

2. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 2/27 Outline Introduction to 3D Motivation Challenges Design Experimental Results Conclusion

3. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 3/27 3D Integration Technology –Stack multiple active layers vertically –Tightly integrate with die to die (d2d) vias Benefits –Routing freedom –Higher performance –Lower power Kiran Puttaswamy, “Designing High-Performance Microprocessors in 3-Dimensional Integration Technology,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, GA, USA, 2007

4. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 4/27 3D Die Stacking Layer 1 Layer 2 Layer 3 Layer 4 Face to Face Back to Back Face to Back Bond Pads

5. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 5/27 3D Assembly Wafer to Wafer Wafer to Die Die to Die

6. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 6/27 3D Integration and Testability CMOS DRAM Analog Technology Level BitLine0 BitLine1 BitLine2 BitLine0 BitLine1 BitLine2 Circuits Level ALU 1 ALU 2 ALU 3 Architecture Level ALU 4

7. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 7/27 Motivation 100% 80% 100% 0% Single Layer Yield Stack Yield 95% 90% 81% 66% 44% 95%

8. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 8/27 Purpose Enable Pre-bond 3D Test Test Strategy Hardware Requirements Secondary Concerns

9. 9/27 Pre-bond Challenges

10. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 10/27 Complete Architectural DesignPossible Pre-bond Partition Fetch Decode Reorder Buffer Issue Out of Order Execution Commit I Cache D Cache Pre-bond Test Challenges Incomplete Circuits Architectural Level Circuit Level Complete Register File DesignPre-bond Circuit 10,000 +

11. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 11/27 Pre-bond Test Challenges Wafer Probing Probing Probe Pads

12. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 12/27 Pre-bond Clock Tree Nets Pre-bond Test Challenges Supporting Nets Power, Ground, Clocks, Etc. Complete Clock Tree Net

13. 13/27 Proposed Solution

14. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 14/27 Test Strategy Alpha 213643D Pre-bond Test IEEE 1149.1 TAP ISP LTC IEEE 1149.1 TAP CSC

15. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 15/27 Layer Border Scan Flops Flags Pipeline Stage Register Low Add High Add Bus From Another LayerBus To Another Layer SiSo Scan Registers Pre-bondPost-bond Test_Enable

16. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 16/27 Scan Flops Not Required Low Add High Add Bus From Another LayerBus To Another Layer SiSo Pre-bondPost-bond Flags Pipeline Stage Register Low Add High Add

17. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 17/27 Test Pads Faceside TestReuse Post-Bond

18. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 18/27 Power and Ground Planar DieDie Stack

19. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 19/27 Clock Routing Power/Routing Optimized Pre-bond Test Optimized Layer 1 Layer 2

20. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 20/27 Real Clock Tree

21. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 21/27 Real 3D Clock Tree Layer 1 Layer 2 Layer 3 Layer 4

22. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 22/27 Testable 3D Clock Tree Layer 1 Layer 2 Layer 3 Layer 4 EN CLK EN

23. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 23/27 More Trees Are Better Pre-bond TestReliability X

24. 24/27 Experiment and Results

25. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 25/27 Experiment Based on 21264 Architecture Floorplanned microarchitecture blocks –Two die layers Determined widths of inter-die buses Laid out scan cell E. Wong and S.-K. Lim. “3D Floorplanning with Thermal Vias.” In Design, Automation, and Test in Europe Proceedings, pp. 878-883, 2006.

26. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 26/27 Results Layer 1 Layer 2 Scan Cell Size75.8 μm 2 Inter-die Vias2397 Scan Cell Count Two cells per via 4794 Area0.363 mm 2 Overhead0.165% ICache FP EU1 IntQ IE U4 IE U2 DCache DTLB IE U1 FPEU2 FP Map DIS LSQ IRF 1 FP RF IMap FPQ BPred IRF2 IE U3 ITLB Mem Ctlr Ftch Dcd BIU

27. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 27/27 Conclusion Pre-bond test a necessity for integrating 10+ layers Pre-bond test can be achieved with current manufacturing technologies and test techniques Area cost is insignificant Clock can be designed to both enable pre-bond test and maximize power savings

28. 28/27 Backup Slides

29. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 29/27 Scan and Non-Neighboring Blocks I Fetch ALU Si So

30. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 30/27 Clock Routing Area 2D Clock3D Clock Equal Wiring Required

31. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 31/27 Clock Routing Area 2D Clock3D Clock 50% More Wire in the Limit

32. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 32/27 Clock Routing Layer 2D Clock3D Clock

33. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 33/27 Die-to-Die Bonding Tezzaron Super-Via™ Standard Planar Die Bulk Silicon Device and Metal Layers Top Layer Metal S. Gupta, M. Hilbert, S. Hong, and R. Patti. “Techniques for Producing 3D ICs with High-Density Interconnect.” In Proceedings of the 21 st International VLSI Multilevel Interconnection Conference, Waikoloa Beach, HI, USA, 2004

34. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 34/27 Die-to-Die Bonding Tezzaron Super-Via™ 1 – Dialectric Fill

35. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 35/27 Die-to-Die Bonding Tezzaron Super-Via™ 2 – Super-Via™ Etch

36. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 36/27 Die-to-Die Bonding Tezzaron Super-Via™ 3 – Barrier Deposition

37. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 37/27 Die-to-Die Bonding Tezzaron Super-Via™ 4 – Connection Etching

38. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 38/27 Die-to-Die Bonding Tezzaron Super-Via™ 5 – Barrier and Cu Deposition

39. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 39/27 Die-to-Die Bonding Tezzaron Super-Via™ 6 – Expose Bond

40. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 40/27 Die-to-Die Bonding Tezzaron Super-Via™ 7 – Bond to Second Layer Thermal Diffusion Bonding

41. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 41/27 Die-to-Die Bonding Tezzaron Super-Via™ 8 – Thin Second Layer Grinding and CMP

42. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 42/27 Die-to-Die Bonding Tezzaron Super-Via™ 9 – Expose Via

43. Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 43/27 Die-to-Die Bonding Tezzaron Super-Via™ 10 – Repeat Pad Construction