Introduction to CMOS Process Integration

Name: Introduction to CMOS Process Integration
Uploaded: 2017-08-22T02:05:14+00:00
Duration: PTM40S55
Channel: Wesley Curtis
Description: Introduction to CMOS Process Integration

Introduction to CMOS Process Integration
Ramzan Mat Ayub; SATF 2005 Introduction to CMOS Process Integration

OVERVIEW: PRODUCT CATEGORY
Ramzan Mat Ayub; SATF 2005 OVERVIEW: PRODUCT CATEGORY 2005 Global market size = RM 235 billion % 5 Opto - electronics • Exotic processes involved; should reconsider as capability increases • 9 Discrete Low margin and scale wins in discrete market; • Fragmented market with no dominant player 16 Analog • Higher margin, especially in niche market • Longer shelf life (~15 years) compared to digital technology • Design dominated by leading design houses 18 Logic • Scale wins in fabrication, dominated by 3 - 5 largest global foundries • Heavy R&D on deep sub - micron technology required Memory • 21 Intense competition, top 5 players have > 70% market share • Low ROIC, large scale require to play 31 MPU • Dominated by Intel, AMD, Motorola and IBM • Continuous large R&D investment required = 100 Source: IDC

OVERVIEW: TECHNOLOGY 2005 ITRS Conclusions;
Ramzan Mat Ayub; SATF 2005 OVERVIEW: TECHNOLOGY 2005 ITRS Conclusions; Despite significant technology challenges, the industry continued to maintain the pace predicted by Moore's Law - the doubling of transistors every two years. Transistor speed continued to improve at the historical improvement rate of 17 percent per year, although the challenges became more complex due to a concurrent increase in leakage currents. Research intensified on major technology innovations like high-k dielectrics, metal gate electrodes, and multiple-gate MOS transistors, which are forecast to enter manufacturing before the end of the decade. These represent major shifts, where some basic device materials and structures will undergo change for the first time in more than 30 years. Mixed-signal and analog chips continue to grow in importance, driven especially by consumer and communications-related markets. State-of-the-art microprocessors now run well in excess of several GHz. Memory designs are geared increasingly to specific applications. And new memory technologies based on totally new concept (spin state, molecular and single electron memory are emerging)

BUSINESS MODEL Foundry (TSMC, UMC, Silterra, 1st Silicon)
Ramzan Mat Ayub; SATF 2005 BUSINESS MODEL Foundry (TSMC, UMC, Silterra, 1st Silicon) – only manufacture Design House (Alterra, MyMS) - only design Integrated Design Manufacturing (Intel, Motorola, IBM, MIMOS) - design and manufacture

Semiconductor Manufacturing Processes
Ramzan Mat Ayub; SATF 2005 Semiconductor Manufacturing Processes Design Mask info to MASK-SHOP + GDSII file Mask making Generate runcard Wafer Preparation Front-end Processes (individual transistor) Deposition Oxidation Diffusion Photolithography Etch (wet and dry) Implantation Backend Process Deposition (oxide, nitride etc) Metalization Rapid Thermal Process Lithography & Etch Test (Parametric and Functional) Packaging

Ramzan Mat Ayub; SATF 2005

Circuit Schematic Layout Silicon VIN vDD VOUT vSS VDD VIN VOUT pMOS
Ramzan Mat Ayub; SATF 2005 Circuit Schematic Layout Silicon VIN pMOS nMOS VDD VSS S D VIN VOUT Poly gate vDD pMOS p+ drain p+ source n+ drain n+ source VOUT nMOS vSS

SILICON COMPONENTS FOR INTEGRATION
Ramzan Mat Ayub; SATF 2005 SILICON COMPONENTS FOR INTEGRATION Contacts Resistors Capacitors P-N Junctions Bipolar Transistors Uni-polar Transistor (FET)

CONTACTS Are made to connect components to the outside world
Ramzan Mat Ayub; SATF 2005 CONTACTS Are made to connect components to the outside world Bad contacts are Non-ohmic, high resistive Leaky Bad contacts can cause circuit failure Main causes for non-ohmic behavior Contaminated interface Incomplete contact etch Low dopant concentration (dopant depletion from Si into silicide Main cause for leaky behavior is metal penetration (Al spiking) Characterized by a parameter called contact resistance (ohm per contact) using test structure called contact chain. Several thousands of contact of different sizes running on different topography. Height of barrier to carrier flow carriers ILD0 AlSiCu GATE Silicon ILD0 AlSiCu GATE Silicon

Ramzan Mat Ayub; SATF 2005 CONTACTS (continue)

CONTACTS (continue) Ohmic Contact
Ramzan Mat Ayub; SATF 2005 CONTACTS (continue) ohmic I Ohmic Contact Formed between metal and heavily doped Si Barrier exist but is very thin Carriers tunnel through the carrier Symmetrical I-V characteristics Non-ohmic behavior High contact resistance Indication of process problem or bad integration Schottky barrier Formed between metal and lightly doped Si Wide barrier Diode I-V characteristics Non-ohmic V I forward BV (>20V) V Vt ( V) reverse

RESISTORS Applications
Ramzan Mat Ayub; SATF 2005 RESISTORS Applications Analog mixed signal (RF & wireless application), when high precision and matching were needed. Current limiter Voltage drop Diffused layer (nwell ~ 1000 ohm per square) and poly-1 (~ 35 ohm per square) normally used as resistors Parasitic resistance transistor / IC speed degradation: RC delay Source and drain region (salicide, halo implant) Contact and via (silicide) Metal lines (copper) LOCOS substrate substrate Poly as resistor Diffused layer as resistor

Ramzan Mat Ayub; SATF 2005 Resistivity Resistivity of n-type material is inversely proportional to donor concentration, ND µn is electron mobility ρ = 1 / q µn ND Resistivity of p-type material is inversely proportional to donor concentration, NA µp is hole mobility ρ = 1 / q µp NA As the temperature increases, the mobility decreases and resistivity increases shorter carriers mean free path due to lattice atoms vibration For the same doping and concentration and temperature, electrons are approximately 3 times mobile (faster) than holes – hence NMOS is 3 times faster than PMOS

Resistance & Sheet Resistance
Ramzan Mat Ayub; SATF 2005 Resistance & Sheet Resistance The resistance of a resistor depends on its resistivity, length and cross-sectional are R = ρ L / A Sheet resistance is the most widely parameters. Is defined as the resistance between two opposite sides of a square of the layer. Unit: ohm / □ Rs = ρ / t

Resistance & Sheet Resistance (continue)
Ramzan Mat Ayub; SATF 2005 Resistance & Sheet Resistance (continue) Typical resistor TOP-VIEW (layout) RESISTOR W L R = Rs x L / (W – ΔW) x Rc / (W – ΔW) Rs – Sheet resistance of resistor ΔW – width reduction due to litho / etch L - Drawn resistor length Rc - contact resistance W – Drawn resistor width

CAPACITORS Applications Memory and logic (DRAM, E/EEPROM memory cell)
Ramzan Mat Ayub; SATF 2005 CAPACITORS Applications Memory and logic (DRAM, E/EEPROM memory cell) Precision analog design MOS process characterization Device characterization, SPICE model extraction and etc. Parasitic capacitance transistor / IC speed degradation: RC delay Low-k dielectrics Thick ILD Good backend planarization (global planarization)

C = A ε0 εi / t CAPACITORS t C – capacitance (F)
Ramzan Mat Ayub; SATF 2005 CAPACITORS Conductor-1 t Insulator Conductor-2 C = A ε0 εi / t C – capacitance (F) A – area common to plates (cm2) ε0 - universal constant (8.86 x F/cm) εi - dielectric constant (oxide=3.9, nitride=7) t - dielectric thickness (cm)

CAPACITORS (continue)
Ramzan Mat Ayub; SATF 2005 CAPACITORS (continue) MIM Capacitor (Metal – Insulator – Metal) TiN, Al t Oxide or nitride TiSi2, Al TiN TiSi2 Poly FOX Parasitic capacitance Silicon substrate

Ramzan Mat Ayub; SATF 2005 CAPACITORS (continue) MIM Capacitor (Metal – Insulator – Metal) TiN TiSi2 Poly FOX Parasitic capacitance Silicon substrate

Ramzan Mat Ayub; SATF 2005 CAPACITORS (continue) MIS / MOS Capacitor (Metal – Insulator – Silicon) Poly, Metal-1 t Oxide or oxynitride n-type or p-type Si S/D FOX GateOx n-well substrate

Ramzan Mat Ayub; SATF 2005 PN JUNCTION Xd P-type + - N-type NO BIAS A pn junction is the boundary between p-type and n-type silicon Region between n and p is depleted from electrons and holes Xd is width of depleted region Depletion region is wider in a lighter doped region. Given NA = 1015 cm-3, ND = 1017 cm-3 For n-type region For p-type region n=1017 cm-3 (why?) p=1015 cm-3 (why?) What is p (hole concentration)? What is n (e concentration) ?

PN JUNCTION (continue)
Ramzan Mat Ayub; SATF 2005 PN JUNCTION (continue) I I forward P + V V - Vt ( V) N reverse forward forward bias – large current electrons are injected into p holes are injected into n reverse bias – small current electrons are extracted from p-side to n-side holes are extracted from n-side to p-side I P - V + N reverse

Ramzan Mat Ayub; SATF 2005 PN JUNCTION (continue) A Effect of resistance A 10-2 10-2 avalanche breakdown 10-5 10-5 IF IR 10-8 10-8 impact ionization 10-11 10-11 Threshold swing leakage > 60mV / 25C 10-14 V V 1 2 10 20 VF VR

Ramzan Mat Ayub; SATF 2005 PN JUNCTION (continue) P N p+ FOX FOX n-well substrate

MOSFETs 4 types of MOSFETs NMOS enhancement mode (normally off)
Ramzan Mat Ayub; SATF 2005 MOSFETs N-source 4 types of MOSFETs NMOS enhancement mode (normally off) depletion mode (normally on) PMOS enhancement mode depletion mode P-well or P-substrate GATE N-drain NMOS P-source Mode of operation To turn on: inversion layer connects S and D To turn off: no inversion between S and D Enhancement mode Inversion layer is initially absent. To turn on, apply Positive voltage on gate of NMOS Negative voltage on gate of PMOS n-well or n-substrate GATE P-drain PMOS

MOSFETs LAYOUT Active Region SOURCE DRAIN WD LD
Ramzan Mat Ayub; SATF 2005 MOSFETs LAYOUT Active Region DRAIN SOURCE WD LD Poly extension over LOCOS Poly Contact Important Note: ALL the dimensions must FOLLOW the Design Rules Metal-1

MOSFETs CROSS SECTION SOURCE DRAIN WD CUT LD PMD or ILD0 Leff
Ramzan Mat Ayub; SATF 2005 MOSFETs CROSS SECTION DRAIN SOURCE WD CUT LD PMD or ILD0 Leff Spacer – for LDD (to suppress the hot electron effect) LOCOS encroachment into active

MOSFETs HOW AN ENHANCEMENT MODE NMOS WORKS
Ramzan Mat Ayub; SATF 2005 MOSFETs HOW AN ENHANCEMENT MODE NMOS WORKS ground VD VG A PMD or ILD0 N+ Drain N+ Source Leff With 0 or negative bias on gate, there is no S to D current With +ve voltage on gate, holes are repelled and e attracted to the surface With sufficient VG, thin sheet of electron forms between S and D S and D are now connected Thin sheet of electrons is called inversion layer Sufficient VG is called Threshold Voltage, VT

MOSFETs HOW AN ENHANCEMENT MODE PMOS WORKS
Ramzan Mat Ayub; SATF 2005 MOSFETs HOW AN ENHANCEMENT MODE PMOS WORKS ground VG VD A PMD or ILD0 P+ Drain P+ Source Leff With 0 or positive bias on gate, there is no S to D current With -ve voltage on gate, electrons are repelled and holes attracted to the surface With sufficient VG, thin sheet of holes forms between S and D S and D are now connected Thin sheet of holes is called inversion layer Sufficient negative VG is called Threshold Voltage, VT

MOSFETs TYPICAL CMOS CROSS SECTION
Ramzan Mat Ayub; SATF 2005 MOSFETs TYPICAL CMOS CROSS SECTION NMOS and PMOS on the same die to form a basic design block for VLSI technology (inverter). Superior than NMOS or PMOS process technology in terms of; Lower power dissipation Design flexibility Compact ability Noise immunity When Vin is high PMOS is off NMOS is on Vout is at ground When Vin is low PMOS is on NMOS is off Vout is at Vdd Vin Vout Vdd Ground FOX DRAIN DRAIN nLDD pLDD pwell nwell NMOS PMOS

CMOS PROCESS INTEGRATION
Ramzan Mat Ayub; SATF 2005 CMOS PROCESS INTEGRATION

Unit processes, modules, integration
Ramzan Mat Ayub; SATF 2005 Unit processes, modules, integration Unit processes development Oxidation, deposition, lithography Etch, diffusion, ion implantation Modules development Gate stacks, well, isolation, source & drain IMD, contacts / interconnect Integrated Process CMOS, BiCMOS, EEPROM Flash, SRAM, DRAM

TYPICAL CMOS PROCESS FLOW
Ramzan Mat Ayub; SATF 2005 TYPICAL CMOS PROCESS FLOW Main Process Modules (CMOS 1P2M 3.3V) Wells Formation Active Area Definition Device Isolation (LOCOS) Vt Adjust Polygate Definition Source & Drain Formation Pre Metal Dielectrics Deposition (PMD) Contact Definition Metal-1 Deposition & Patterning Inter-Metal Dielectrics Deposition (IMD) Via Definition Metal-2 Deposition & Patterning Passivation Pad Definition FRONT END PROCESS (creating an electrically isolated devices) BACK END PROCESS (connecting the devices to form the desired circuit function.) Full integration may require process steps

DEVICE ISOLATION TECHNOLOGY
Ramzan Mat Ayub; SATF 2005 DEVICE ISOLATION TECHNOLOGY Electric circuit in VLSI technology is implemented by connecting isolated devices through specific conducting path. To fabricate monolithic ICs, electrically isolated devices must be created in the silicon substrate. Only later they are connected. Improper isolated device will result; total circuit failure high leakage (large dc power dissipation) noise margin degradation voltage shift, cross talk between transistors and etc. The challenge is VLSI device only allows single transistor leakage < 10 pA/um). On the other hand, process integration imposed a stringent requirement on the isolation technology; spacing between actives should be as small as possible to produce the surface topography as planar as possible isolation process module must be simple to implement and easy to control

Ramzan Mat Ayub; SATF 2005 DEVICE ISOLATION TECHNOLOGY MOS Device Isolation Characteristics MOS transistors are self isolated as long as; The source-substrate and drain-substrate pn junctions are held at reverse bias Reverse bias drain-substrate leakage should be negligible Insignificant drain-source current during OFF state Parasitic channels are prevented from forming among adjacent devices Negligible leakage current between adjacent MOS devices

Ramzan Mat Ayub; SATF 2005 DEVICE ISOLATION TECHNOLOGY MOS Device Isolation Characteristics VTF is the threshold (minimum) voltage to turn on the parasitic MOS (field transistor) 2 methods of increasing the VTF; making a thicker field oxide Increase the doping beneath field oxide (channel stop implant) Field transistor M-1 DRAIN SOURCE NMOS#1 NMOS#2

Ramzan Mat Ayub; SATF 2005 DEVICE ISOLATION TECHNOLOGY Isolation technique in CMOS Grow and etch thick oxide Semi recessed LOCOS Conventional Poly buffered SILO and etc Fully recessed Trench a) Grow and Etch oxidation oxidation nitride removal nitride removal b) Semi recessed LOCOS c) Fully recessed LOCOS

Ramzan Mat Ayub; SATF 2005 DEVICE ISOLATION TECHNOLOGY Grow and etch (used until late 70s) Thick oxide is grown thermally in the furnace Wafer is patterned and etch Disadvantages Sharp corners, difficult to cover in the latter process steps Channel stop must be implanted before oxide is grown (active to be aligned with channel stop region – low packing density)

Ramzan Mat Ayub; SATF 2005 DEVICE ISOLATION TECHNOLOGY B) Semi-recessed LOCOS Conventional LOCOS 20-60nm oxide is grown [pad oxide]-to cushion stress of nitride nm CVD nitride is deposited as oxidation mask. Nitride is very good in this as oxygen and water vapor diffuse very slow through it. But very high tensile stress Mask to define active regions Channel stop implant – desirable to implant after LOCOS oxidation Grown thick oxide using wet oxidation Boron segregation and lateral diffusion Bird’s beak Strip oxide and nitride using wet etch

Ramzan Mat Ayub; SATF 2005 DEVICE ISOLATION TECHNOLOGY C) Advance Semi recessed LOCOS Etch back LOCOS The simplest way to reduce bird’s beak A portion of LOCOS is etched after oxidation b) Poly buffered LOCOS Use thinner pad oxide [poly 50nm,oxide 10nm] and thicker nitride Solve the bird’s beak issue, do not solve planarization. Fully recessed LOCOS Quiz: Write an essay on a Fully recessed LOCOS isolation technology used in CMOS wafer fabrication process.

Ramzan Mat Ayub; SATF 2005 DEVICE ISOLATION TECHNOLOGY Integration Issues with Thermally Grown Oxides Contamination, ionized impurities Bulk & interface traps Pinholes Uniformity Thermal budget Induced defects Impact on dopant profile Stress

Ramzan Mat Ayub; SATF 2005 DEVICE ISOLATION TECHNOLOGY E) Trench Technology 4 major applications Locos replacement for isolation within the well Isolation in bipolar Latch prevention in CMOS Trench capacitor in DRAM 3 categories Shallow trench <1 um Moderate 1-3 um Deep >3um deep Advantages Increase the packing density tremendously Disadvantages Complex to fabricate, very expensive machines Poor uniformity Low throughput Trench etched CVD oxide deposited Oxide polished to surface by CMP

WHY MULTILEVEL INTERCONNECT???
Ramzan Mat Ayub; SATF 2005 MULTI LEVEL INTERCONNECT TECHNOLOGY The requirement is to connect the device electrically at the later stages of wafer fabrication in order to implement the desired circuit functionality. 2 major components Multilevel Metallization Multilevel Dielectrics WHY MULTILEVEL INTERCONNECT??? Contribute to ~75% low yield problem

MULTI LEVEL INTERCONNECT TECHNOLOGY
Ramzan Mat Ayub; SATF 2005 MULTI LEVEL INTERCONNECT TECHNOLOGY Nomenclature in IC Application

Ramzan Mat Ayub; SATF 2005 MULTI LEVEL INTERCONNECT TECHNOLOGY

Ramzan Mat Ayub; SATF 2005 MULTI LEVEL INTERCONNECT TECHNOLOGY MULTILEVEL METALIZATION General Requirement Low resistance materials Low contact resistance Electrically stable Good step coverage (bottom and sidewall) for non plug process Process compatibility and cost effective Stress Adhesion to oxide Electro migration Easiness to pattern and etch good W Film bad

Ramzan Mat Ayub; SATF 2005 MULTI LEVEL INTERCONNECT TECHNOLOGY Materials and Application ρ (-cm) 5000A Material Application Technology ( m) Al, AlSiCu Interconnect 1.0, 0.5, 0.35 2.65 Cu Interconnect 0.25, 0.18 1.67 Ti Adhesion (Al, Cu) 0.5, 0.35, 0.25 43 TiN Barrier, ARC 0.5, 0.35, 0.25 25 TiW Adhesion (W) 0.5, 0.35, 0.25 75 W Via Plug 0.5, 0.35 6

Ramzan Mat Ayub; SATF 2005 MULTI LEVEL INTERCONNECT TECHNOLOGY General Conclusions Aluminum still the metal of choice High conductivity Process compatibility Al drawback Electro migration due to small grain size. Add copper (1-1.5%) Incompatible with >500C process Copper Higher conductivity than Al Better electro migration resistance Difficult to etch. To use other difficult technique (damascene process)

Ramzan Mat Ayub; SATF 2005 MULTI LEVEL INTERCONNECT TECHNOLOGY MULTILEVEL DIELECTRICS General Requirement Ability to electrically isolate two levels of metal Ability to planarise, minimize the possibility of open circuits for the subsequent metal Chemical and thermal stability during subsequent process step Repeatable and reliable Good adhesion to underlying layers Ability to produce layers of varying thickness Process compatibility Deposition temperature Low k

Ramzan Mat Ayub; SATF 2005 MULTI LEVEL INTERCONNECT TECHNOLOGY MULTILEVEL DIELECTRICS Dielectric Materials CVD oxide C PECVD oxide / nitride C SOG C , 450C cure Polyimide C, 400C cure Planarization Methods Deposit and etch-back Deposit and CMP

Ramzan Mat Ayub; SATF 2005 MULTI LEVEL INTERCONNECT TECHNOLOGY Major Reliability Issues Metalization ESD electro migration Latch-up stress corrosion Transistors hot carrier effects Junctions leakage, shorts Dielectrics leakage breakdown, surface states, traps

FUTURE TRENDS/ISSUES IN INTEGRATION
Ramzan Mat Ayub; SATF 2005 FUTURE TRENDS/ISSUES IN INTEGRATION

Ramzan Mat Ayub; SATF 2005

Introduction to CMOS Process Integration

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