1. © 2008 Altera Corporation—Public Why You’ll Want to Think Altera When You Think About Your Next Embedded System

2. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2 Agenda Why developers choose Nios ® II processors Nios II Embedded Evaluation Kit (NEEK) demo— a real example Nios II performance System integration using Altera ® embedded technology Resources available Conclusion

3. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3 There are more soft cores than hard cores in the FPGA market Gartner believes that Altera is shipping the most soft processor cores in FPGAs (Nios processor and, more recently, ARM ® ) Estimated FPGA/PLD Design Starts, Worldwide, 1999-2011 20,000 40,000 60,000 80,000 100,000 102,000 107,100 94,248 84,823 80,582 83,000 84,102 85,532 87,756 90,125 92,378 95,704 100,010 With microprocessor core Source: Gartner Dataquest Without microprocessor core

4. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 4 Why Developers Choose Nios II Processors Custom fit to users’ application Works with all Altera FPGA devices Scalable performance Concept to system in minutes

5. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 5 Nios II Processor - World’s Most Popular Soft Processor Over 20,000 development kits shipped  Used in communications, consumer, industrial, medical, automotive, and broadcast products worldwide  Used by all of the top 20 OEMs Active Nios design community (www.niosforum.org)  Over 8,000 active members

6. © 2008 Altera Corporation—Public Nios II Embedded Evaluation Kit (NEEK): A Real Example

7. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 7 Nios II Evaluation Kit - Hardware Cyclone ® III EP3C25 FPGA Drop-in design examples included on SD card Great out-of-box experience for software developers Only USD $449 Only USD $449

8. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 8 Nios II Evaluation Kit - Hardware Cyclone III starter board  EP3C25 FPGA  32-MByte DDR  1-MByte SSRAM  16-MByte flash  USB-Blaster™ circuitry  JTAG header  HSMC connector Only USD $449 Only USD $449

9. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 9 Nios II Evaluation Kit - Hardware Multimedia board  Color touch-panel LCD  800 x 480 resolution  Composite video input  VGA output  Audio input  Microphone input  Audio output  SD card I/F  10/100 Ethernet (PHY)  PS2  RS-232 Only USD $449 Only USD $449

10. © 2008 Altera Corporation—Public Nios II Performance

11. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 11 Performance Range * Dhrystone 2.1 Benchmark MIPS 0 50 100 150 200 250 300 Nios II/e processorNios II/s processorNios II/f processor Performance (DMIPS*)

12. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 12 Device family Nios II/f processor Nios II/s processor Nios II/e processor Stratix ® III FPGA30012850 Stratix II FPGA25111044 Stratix FPGA1688227 Hardcopy ® Stratix II device22812949 Hardcopy Stratix device1668427 Cyclone III FPGA1656817 Cyclone II FPGA1445518 Cyclone FPGA1305317 Nios II Processor Performance (DMIPS)

13. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 13 External CPU or DSP External CPU or DSP 3 Ways to Scale Performance Multi-processor system PCI FPGA CPU Custom instructions FPGA Hardware accelerators FPGA CPU Hardware accelerator Hardware accelerator Hardware accelerator Hardware accelerator CPU Custom instructions Custom instructions Add processors (internal and/or external) Accelerate individual CPU performance (add application- specific instructions) Accelerate data transformation algorithms with application-specific hardware

14. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 14 Custom Instructions * Example: CRC 64-KByte buffer 0 40 60 80 100 120 Iterations/second Software only Custom instruction 20 27X faster 27X faster Out << >> & Custom logic +-+- A B Nios II embedded processor Extends CPU performance  CPU fetches data, stores results  Ideal for math and logical operations e.g., floating point, bit manipulation  Hardware much faster than software

15. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 15 Hardware Accelerators * Example: CRC 64-KByte buffer CRC coprocessor CRC coprocessor Program memory CPU Data memory Arbiter Data memory Arbiter Coprocessor 0 5,000 1,000 1,500 2,000 2,500 Iterations/second Software only Custom instruction 530X faster Concurrent data coprocessing  CPU starts/stops the coprocessor  Coprocessor fetches data and stores results  CPU runs application code concurrently  Ideal for block data operations

16. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 16 Automates creation and integration of hardware accelerators Intuitive user interface streamlines C acceleration Uses familiar Nios II IDE Support for standard ANSI C language Right-click to accelerate Nios II C-to-Hardware Acceleration Compiler

17. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 17 C-to-Hardware Acceleration main () { …variable declarations… init(); while (!error && got_data()) { do_user_interface(); gather_statistics(); if (got_new_data()) d_transform(in_buf, out_buf); check_for_errors(); } cleanup(); } Execution time

18. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 18 main () { …variable declarations… init(); while (!error && got_data()) { do_user_interface(); gather_statistics(); if (got_new_data()) d_transform(in_buf, out_buf); check_for_errors(); } cleanup(); } Execution time d_transform Right-Click to Accelerate Function

19. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 19 Nios II MHz Accelerate Only What’s Needed µP Tasks 0%100% Time budget Nios II processor Accelerator Transfer processing from CPU to hardware (95-MHz Nios processor with C2H Accelerator performs image rotation as fast as 1.4 GHz processor)

20. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 20 High performance  Multi-processor  Hardware acceleration  Custom instructions  Automated system generation  Hardware/software balance  Fast prototype  production Greatest flexibility Greatest flexibility Powerful design tools Fastest time to market Fastest time to market  Processors  Peripherals  Optimized interconnect  On-chip processor debug  SignalTap ® II logic analyzer  Real-time trace capability Nios II Processor - Leading the Industry

21. © 2008 Altera Corporation—Public System Integration Using Altera Embedded Technology

22. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 22 Flash SDRAM CPU DSP I/O CPU I/O FPGA I/O CPU DSP Overcome System Design Challenges FPGA Too expensive, need to reduce cost Changing standard requires new device, redesign board Marketing requires new features to stay competitive Need to reduce board size to meet form factor requirements 16-week lead time, must qualify 2 nd source Obsolete in 2 years, must support for 7

23. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 23 Flash SDRAM CPU DSP I/O CPU I/O FPGA I/O CPU DSP Solution: integrate external devices within programmable device CPU System Design Challenges

24. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 24 Flash SDRAM FPGA System-Level Integration

25. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 25 First Step in System Design

26. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 26 SOPC Builder – System Generation Tool Companion chip Custom SPI+ SPI General- purpose processor Bus I/F UART PCI Bridge Custom General- purpose processor Bus I/F UART PCI ASSPSystemDevice Multi-processor Custom General- purpose processor Bus I/F UART PCI SPI Ethernet Custom microcontroller Ethernet RAM UART SPICustom

27. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 27 SOPC Builder System Design Cuts weeks off development time 1. Select and configure IP2. Select connections3. Generate system HDL simulator FPGA

28. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 28 DMA Read _ Master Write _Master Control port slave Nios II Processor Data _Master Instruction _Master ETHERNET_MAC DMA _Master Igor_the _Slave SDRAM Onchip_ Memory UARTTIMERGPIO SOPC Builder automatically generates system interconnect fabric Building a SOPC System

29. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 29 Demo – SOPC Builder Goal (in 10 minutes)  Show how easy it is to build a system with SOPC Builder  Show how easy it is to add a custom component to your system Overview  Using SOPC Builder, we will build a system from scratch. The system will include a processor, memory, Ethernet, and USB Basic steps 1. Create a new Quartus II project 2. Create a new SOPC-based system 3. Add a Nios II processor to system (repeat for memory, Ethernet) 4. Add custom component – USB 5. View generated system in Quartus II software

30. © 2008 Altera Corporation—Public Resources Available

31. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 31 GNU tools debugger, C/C++Compiler Nios II Embedded Design Suite Integrated software development: manage, build, debug Peripheral drivers and run-time software library Embedded Design Suite IDE HAL API Command line- based software build flow

32. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 32 * Full evaluation included in kit &/or web download - license sold separately Nios II Embedded Design Suite C to Hardware (C2H) Compiler* Real-time operating system from Micrium* Commercial-grade network stack from Interniche* Embedded Design Suite Advanced debugging tools from FS2 and Lauterbach*

33. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 33 Nios II Hardware Abstraction Layer (HAL) The HAL provides a simple device driver interface to communicate with hardware _exit() close() closedir() fstat() getpid() gettimeofday() ioctl() isatty() kill() lseek() open() opendir read() readdir() rewinddir() sbrk() settimeofday() stat() usleep() wait() write() HAL API Nios II processor system hardware Device driver … HAL API Shared library User program HAL benefits  Change your hardware without having to change your software code  When hardware is generated, a matching custom software BSP is created automatically

34. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 34 Operating Systems Company nameOS Nios II IDE Plug-In Real timeType eCosCentriceCos- Open source EurosEuros RTOS- Commercial EvidenceErika Enterprise Commercial Express LogicThreadX Commercial Mentor Graphics ® Nucleus Plus- Commercial MicriumMicroC/OS-II Commercial MicrotronixµCLinux -Open source SeggerembOS- Commercial VectorosCAN - Commercial Community Supported (www.niosforum.org)www.niosforum.org µCLinux -Open source For more information go to Operating Systems under www.altera.com.cn/embedded www.altera.com.cn/embedded

35. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 35 Nios II Technical Documentation Extensive literature section on Altera.com  Nios II Software Developer’s Handbook  Nios II Processor Reference Handbook  Tutorials  Application notes Nios II processor design examples  Ethernet  Multiprocessor  PLL tuning  Web server  and many more Nios forum (www.niosforum.com)  7000+ registered Nios II users  Over 5,800 topics Nios Wiki (nioswiki.jot.com)  Nearly 100 pages of Nios II user-generated documentation

36. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 36 Optimizing C Compiler Partner Software Development Tools Nucleus RTOS

37. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 37 Conclusion Developers choose Nios II processors because of customization, flexibility, and time to market NEEK demonstrates what Nios II processor can accomplish Nios II performance ranges from 17-300 DMIPS SOPC Builder makes system integration easier