1. RH850 & RL78 - Next Generation of Automotive Microcontrollers

2. Renesas Technology & Solution Portfolio
The wealth of technology you see here is a direct result of the fact that Renesas Electronics Corporation was formed on April 1, 2010 as a joint venture between Renesas Technology and NEC Electronics — Renesas Technology having been launched seven years ago by Hitachi, Ltd. and Mitsubishi Electric Corporation. There are four major areas where Renesas offers distinct technology advantage.
--The Microcontrollers and Microprocessors are the back bone of the new company. Renesas is the undisputed leader in this area with 31% of W/W market share.
--We do have a rich portfolio of Analog and power devices. Renesas has the #1 market share in low voltage MOSFET solutions.
--We have a rich portfolio of ASIC solution with an advanced 90nm, 65nm, 40nm and 28nm processes. The key solutions are for the Smart Grid, Integrated Power Management and Networking
--ASSP: Industry leader for USB 2.0 and USB 3.0. Solutions for the cell phone market
-- Memory: #1 in the Networking Memory market

3. Microcontroller and Microprocessor Line-up
2010
2012
32-Bit High Performance,
High Scalability & High Reliability
1200 DMIPS, Superscalar
1200 DMIPS, Performance
Automotive & Industrial, 65nm
600µA/MHz, 1.5µA standby
Automotive, 40nm
500µA/MHz, 35µA deep standby
500 DMIPS, Low Power
32-bit
Automotive & Industrial, 90nm
600µA/MHz, 1.5µA standby
8/16-Bit True Low Power
High Efficiency & Integration
165 DMIPS, FPU, DSC
165 DMIPS, FPU, DSC
Industrial, 90nm
500µA/MHz, 1.6µA deep standby
Industrial, 40nm
200µA/MHz, 0.3µA deep standby
Those of you who have attended the last DevCon in 2010, the left side of this slide should look familiar. In 2010, as a result of the merger between Renesas Technology and NEC Electronics, we started offering MCU solutions based on these five cores. The R8C and 78K were mainly focusing on low end 8/16 bit applications in both automotive and industrial applications,. The RX with 32 bit CISC core was mainly offering solutions for Industrial and consumer applications.  The high-end V850 and SH cores with 32-bit RISC architecture were very successful in high end automotive and industrial applications.
Within 6 months after the merger, we launched a brand new 16-bit product family named RL78, combining the low power flash technology and the CPU core from NEC’s 78K product line and innovative peripherals from Renesas’ R8C product family. The RL78 family is a great example of the synergy effect of this merger. The RL78 is now our main focus product line for cost sensitive low power applications. It consumes only 144uA/MHz power in active mode and only 0.2uA in standby mode. With up to 44DMIPS throughput, it offers much higher performance compared to any other 8/16 microcontrollers in the market place.
The RX family continues to be our flagship 32-bit family for Industrial and consumer applications. With 100 MHz single cycle flash, 1.65DMIPS/MHz throughput and packed with connectivity peripherals it  is ideal for digital signal controller applications. Since its introduction in 2009, we are rapidly expanding the RX product line. Now we have more than 500 different RX MCUs covering from 32KB to 2MB flash memory options.
Similar to the RX, we have recently announced the launch of our next generation high-end 32 bit microcontroller architecture for automotive applications. The new family is called RH850 and provides a next-generation migration path to automotive customers currently using V850 or SH in their application. For Industrial customers currently using V850 or SH, the migration path is the RX product family. Very soon we will launch a 240MHz RX product line which can cover the need of Industrial customers requiring more than 100MHz performance.
So, in summary, from 2013 and beyond, we will mainly be focusing on the three CPU cores, RL78, RX, and RH850, to cover the broad spectrum of the industrial and automotive application space, and we will continue to support legacy architectures like R8C, 78K, SH, and V850 for existing customers.  
25 DMIPS, Low Power
Industrial & Automotive, 150nm
190µA/MHz, 0.3µA standby
44 DMIPS, True Low Power
8/16-bit
Industrial & Automotive, 130nm
144µA/MHz, 0.2µA standby
10 DMIPS, Capacitive Touch
Industrial & Automotive, 130nm
350µA/MHz, 1µA standby
Wide Format LCDs

4. ‘Enabling The Smart Society’
Challenge: “How to meet the next generation of automotive MCU real time control requirements while at the same time meeting green requirements and “Smart Car” vehicle evolutions which OEMs and consumer are demanding.
Solution:
This class will introduce Renesas’ next generation of Automotive MCUs and show they meet demands of vehicle OEMs real time control systems and Green and “Smart car” goals.
CAN
In the session 1C06B, RH850 & RL78 - Next Generation of Automotive Microcontrollers., Paul Kanan introduces this high level of the RH850 and RL78 MCU for the Automotive Market

5. Agenda Automotive Trends Goals for Next Generation MCU Design
Performance vs. Power Consumption
Flash Memory Challenges and Renesas Response
Advance Networking and Security IP
Functional Safety Considerations
Roadmaps

6. Automotive Trends

7. Macro Trends - Energy Lower weight options Smaller vehicles
Architectures considering HEV and electric vehicle options
More efficient, greener. flexible fuel engines
Stricter Fuel economy standards: (Euro6; CAFÉ)
Notes: Macro Trend- Energy
1.) OEM are always looking or new ways to lower weight. The FTC (Federal Trade commission) estimates that every of 100 1bs can increase fuel economy by up to 2% (
OEMs look to save weigh (within Electrical Architecture) by:
a.) reducing wire harness;
b.) integration Module functionality to remove additional housing.
Of course this is also necessary as NA consumers demand smaller cars (less vehicle real estate) as well.
2.) New powertrain and electrical architectures are under development
a.) Maximizing battery life is (for HEV and EV) are very strategic and marketable items for OEMs
b.) Flexilble Engine to support flexible fuels… -- This affect Direct injection strategies which affects Engine control ECUs
E.G. Brazil engines need to operate with both Sugar can base Ethanol and traditional Gasoline. To support f lex vehicle a small gasoline reserve is used to cold starts (< 15C).
3.) Government seizing the opportunity to control something else; are now make more strict requirements to reduce CO2 and meeting very stringent CAFÉ (Corporate Average Fuel Ecocomy standards.)

8. Macro Trends – Consumer Demand
More convenience items
Integrated functions
More safety and security
More horse power & better gas mileage
Intuitive functionality
Connectivity
Notes: Macro Trend- Consumer Demand
1.) Car are becoming extensions of the individual. Request for customization (Ambient lighting) and heated/cooled seat; self parking
2.) Higher take rate of feature leads to integration;
3.) Consumer and governments are demanding more safety and security;
Dense city population and driver distraction lead to new demands for object detection and pedestrian protection
4.) How vehicles HMI are changing… Consumers want intuitive control
5.) Consumer never want to loose connectivity; even for short drives

9. Embedded System Trends
Increase in MCU performance
Increase in Flash Memory
Advanced Networking
&.
Lower current draw
Safety as Value Added
Security concerns
&.
&.
Higher Device Performance  From Macro Trends Energy  we see more sophisticated power trains
 From Macro Trend Consumer  we see more demands or safety; integration of modules
At the same time we have demands for lower current
Lower Device Current Draw  From Macro Trends Energy  more demand for MPGs and extended Battery life (EV)
 From Macro Trend Consumer  saving money on fuel cost huge demands
Larger Memory  From Macro Trends Energy  Addition of new Features and Functions
 From Macro Trend Consumer  Integration to save space and fuel
Networking  From Macro Trends Energy  Vehicle network backbones are being re-architected to optimize loading and distribute power. Addition of LIN networks; increase in CAN networks; FlexRay; Ethernet and USB are all options for next generation vehicles.
Security  As more networks are introduced there are more attack points more; protecting critical system for vehicle security and safety are demanded. ‘
Safety  With ISO2626 Electrical device need to be designed for to be safe; this include embedded redundancy, diversity inlcuding self tests.
Creating Technologies and Designing MCUs Which Meet These Trends is our Challenge!

10. Goals of the New Generation of 32-bit MCU
High Performance
High performance CPU
Multi core
High-speed Flash access
Better MIPS/mA
Advanced Peripherals
Advanced eco-system
High Reliability
Security feature
Functional safety
Highｰtemperature
operation
High Scalability
No Speaker notes needed.
Scalable architectures
Scalable peripherals
Compatibility from low to high

11. New Generation of 16-bit MCU
True
Low Power
Comprehensive
Tools And Support
Broad
Scalability
High Quality
And Safety
High
Performance
Ultra Low Power:
1.) RL78 offers very low power MCU operation with 140uA/MHZ power consumption at 32MHZ, which puts RL78 into the “Best-In-Class” category for the 16bit MCU world.
2.) In Stop/Halt mode the standby current is 0.32uA typical with LVD enabled while retaining all RAM contents..
3.) Snooze Mode further conserves current by allowing the ADC block or Serial (SPI/CSI or UART) unit to start up out of STOP mode without CPU intervention while data is being captured.
Extensive scalability:
RL78 gives designers nimble flexibility over multiple pin counts from 20 to 144pin and memory sizes from 8KB to 512KB Flash.
High Performance:
1.) RL78 performance is up to MHZ, consuming only 5.1mA typical.
2.) The RL78 series offers a wide voltage operating range from +1.8V up to +5.5V.
System Cost Reduction;
High integration and advanced peripherals reduces System Costs by eliminating components previously implemented externally.
1.) Data Flash with Background operation eliminates the need for external EEPROM. The Data flash is targeted for 1 milliion Erase/Write cycles to match the life of external EEPROM.
2.) High speed oscillators with +/-1.5% Frequency accuracy are rated over the full voltage (1.8V to 5.5V) and full temp range (-40C to +125C), and can be further trimmed with a calibration register.
3.) The 10bit ADC offer a wide voltage operation range with +/-2 LSB typical accuracy over the full voltage and temp range. The ADC also has self-test features to compare the external reference pins against MCU input voltages and other ADC reference voltages.
High Quality and Safety;
1.) ECC on every 32bit Flash Word gives instruction/data resilience to the Flash memory contents decades after Flash memory is initially programmed.
2.) 16bit CRC function block can find gross errors, and record the error, so that the MCU to be shut down safely.
3. )Internal RAM and registers can also be write protected against rogue, run-away code operation by locking that memory space against unauthorized writes.
4.) The system clock oscillator can also be checked for erroneous frequency generation by the Timer safety function. Thus, SW architects can detect faults and direct the MCU to shut down to a safe, inert mode.
Rich Ecosystem:
1.) RL78 MCU designs are enabled by Industry-standard development Tools, such as the free GNU and Eclipse Compiler SW.
3rd Party support , like the IAR SW tool chain, allows developers to re-use their knowledge base and SW libraries from previously used MCU platforms.
System
Cost Reduction
* Subject to device

12. Renesas 16 and 32-bit Automotive MCUs
Performance #1
32b & 16b Automotive MCU supplier in the World*
RH850 Real time embedded controls – Covers the following applications
Engine/Powertrain controls
HEV /Traction Control
Chassis/ Power steering/ ABS / Domain control
Restraint controls
F – is for Body or “Frame”
- Since RL is mainly intended for low end body application it also has “F” as it’s catogory
RL78 also has some other specialized functions
- Excellent for low cost BLDC applications
- With hi temp support of 150c Can be used in other applications as “secondary MCU”
- Increasing usage as LIN slaves.
X- Axis can show a number of different items
- Flash
- Current Draw
- Cost
- Embedded Safety
BLDC Motor
*Source: Gartner, " Market Share Semiconductor Devices Worldwide 2010"　30 March 2011 Chart created by Renesas Technology based on Gartner data.
Renesas Technology's MCU revenues in the 1st quarter (Jan. - Mar.) of 2010 has been combined in Renesas Electronics‘ MCU revenues in 2010.

13. Performance and Power Consumption

14. More Performance – 32-bit CPU Core Roadmap
Succession of “850” Architecture
High Performance and Low power
G3M
+FPU(IEEE )
+Branch prediction,
+SIMD,
+Multi-Core
V850E2M
+MPU
V850E2R
+FPU
V850E2
* 7-Stage
* dual-issue
Good Performance and Low Power
Key Points
1.) V850 RISC Architecture
RH850 High performance, high code efficiency by 16/32/48 bit variable instructions
Building on success of proven V850 Core
7 –Stage pipe
FPU
Advance SIMD and branch prediction
Multi core support.
2.) We are continuing to develop a Good performance / Low power core w/ 5 stages pipe focusing on reducing transistor count and reducing power.
V850E1
* 5-stage
G3K
* 5-stage
V850 Architecture
E2S
* 5-stage

15. G3M & G3K 32-bit core characteristics
G3M- Real-time supports w/ improved data processing performance
G3K- Small core with high performance and low-power
■7 Stage Dual issue Pipeline(G3M)
■Difference of ISA IF IT
(B.P.) IP ID EX
(ALU) WB ID EX
(ALU) EX
(LD/ST) WB
SIMD
Inst.
n/a
Non Blocking Buffer EX
(DIV/MUL/FPU)
Cache
Inst.
n/a
EX (SIMD)
(Option)
Multi-core
Inst.
n/a
7 Stage pipeline
1.) During Instruction Transfer (IT)… the New G3M CPU offers Branch prediction; this increases the probability that when a branch is executed the pipeline will not have to be re-loaded.
2.) The dual issue can begin after instruction paring stage
3.) Also the G3M core offers SIMD (Simultaneous Data ) instructions where one instruction can be performed on multiple data.
4.) The G3M also has support for FPU and Multi core instructions.
5 stage pipeline is a low cost and lower power core
1.) Share the same basic instruction w/ G3M
FPU
Inst.
FPU Inst.
(Option)
■5 Stage Pipeline(G3K)
simplify
Basic
Basic IF ID EX
(ALU) EX
(LD/ST/MUL) WB
G3M
G3K
Optimized pipeline structure CPU Freq.
EX(FPU)
(Option)
ISA: Instruction Set Architecture

16. RH850 Architecture (Example CPU Core and Pipeline)
Example RH850 CPU
5-STAGE PIPELINE
96 MHz CPU Core 2.x DMIPS/MHz
5-STAGE PIPELINE
TICK F D F
TICK E D F
TICK M E D F
TICK W M E D F
TICK F W M E D
TICK D F W M E
TICK E D F W M
TICK M E D F W
TICK
Flash Memory
Capable to Flash 120 MHz
SRAM
Memory Protect Unit
Interrupt Control
On-Chip Debug
32x 32bit General Purpose Registers
Inst
128 bit path Instruction
Data
39 bit path Operand (Data)
HARVARD ARCHITECTURE F D E M W E W M E D F E
Que 1
Que 2
32bit Floating Point Unit
(Optional)
Achieves :
One Clock-Per-Instruction (CPI)
32x MAC, b Result
HARVARD ARCHITECTURE
Example of G3K core running at 96MHz… which is ~2DMIPS /MHz… roughly 190DMIPs
FPU option has been develop (not implemented) for more performance or for model based development
32b MAC instruction
32b multiply and divide
We also include 2 x 128b instruction queues, which can hold up to 16 instructions. Mainstream
By Third cycle we have achieved 1 execution per cycle; by the 5 stage pipeline is filled.
With the Harvard architecture since instruction and memory bus are separated the CPU has greater capability to perform multiple operation within one time quanta.
32 x 32 DIV or MULT, 32bit or 64bit Result

17. RH850 Architecture … System Interface
RH850 MCU
PIPELINE
Buffer
RH850
128b instruction
64 bits
128b INST
BUFFER
32b DATA
32 bits
SRAM, up to 120MHz Access
Flash Memory, up to 120MHz Access
Bus Master
Internal Main Bus 1/ System interconnect
32 bits
Bus Bridge
Bus Bridge
DMAC (bus master)
This diagram demonstrates the near simultaneous activity which can take place.
1.) Flash access
2.) RAM Access
3.) CPU peripheral control
4.) DMA transfer of data
5.) Advanced peripherals (CSI, LIN) which are hardware assisted
Peripheral Busses to Spread Bandwidth Loading
Communication (CSI, CAN, SCI,LIN, I2C, Flex Ray)
Timers (TAUA, TAU J, OST, CMT)
Analog
GPIO
System Control (DMA, E2P, ICU, LVD, RTC, WDG, CLKS)

18. 32-bit Multi-Core Architectures for Automotive
Scalable core for both performance and safety
CPU 1
CPU1’
Compare
CPU 2
Compare
CPU2’
Double Redundant Core (“Quad Core”)
Safety
CPU 1
CPU1’
Compare
CPU 1
CPU1’
Compare
CPU 2
Redundant Core
Redundant + Performance Core
CPU 1
CPU 1
CPU2
CPU 1
CPU2
CPU3
Single Core
Dual Core
Triple Core
Performance

19. RH850: 40nm MCU Series for Vehicle Control
High
Mid
Low
Powertrain
320MHz
Dual core w/ Lockstep
I/O CPU
240MHz
Dual core w/LS
I/O processor
160MHz
Single core w/LS
240MHz
Dual core w/ LS
240MHz
Single core w/ LS
High
Reliability
Platform
EV/HEV
240MHz
Dual core w/ LS x2
240MHz
Single core w/ LS
160MHz
Single Core
Chassis &
Safety
240MHz
Single core w/ LS
Low Power
Platform
100 MHz
Single core
Low Power
80MHz
Single Core
Low Power
Air Bag
For the different 32b application spaces we have different core performance requirements.
Within each of these application spaces the product line can cover high to low end performance requirements to fulfill the diverse customer requirements.
One particular interesting item is that we are introducing a specific MCU product dedicated to HEV/EV applications. The unique requirement of HEV traction motor controls are driving this development.
120MHz
Multi Core
Low Cyclic Power
120 MHz
Single Core
Low Power
80 MHz
Single Core
Low Power
Body

20. Low Power Consumption – RUN Mode
RH850: No. 1 in power consumption for Run Mode
mA (Typ.)
mA/MHz 80 70
1.1
64MHz 60
0.9
Next generation will be leading edge runtime power consumption. Here are our targets for RH850/F1L running at 80MHz. This is much lower than the PPC class in 90nm at 64MHz. 50
0.7 40
0.5
80MHz 30
0.3
PPC
90nm
RH850
40nm

21. DeepSTOP F1x estimated current consumption (typ)
STOP mode 200uA – Done through Clock Gating
Deep STOP 35uA – Utilizing Power Domain
ISO area is powered off in Deep STOP
Only 17.5% current
Both Clock gating low power modes and Domain power modes are available.
As you can see during using power domain strategy of DEEPSTOP you will significantly reduce overall power consumption.
DEEPSTOP implementation is to remove power from CPU, Flash memory, most peripherals, and most SRAM. Power is applied to an Always On (AWO )area which consists of timer channels, a couple ports, Key returns, independent watchdog, and oscillator circuits.

22. Low Power Consumption - Standby Mode
RH850: Excellent power consumption for Low Power Mode , Cyclic Wake Up
uA- Avg
210
Reference : F1L - Cyclic 50 ms
digital & analog IO and UART/LIN evaluation.
200uA
Target
180
150
120
Considering when in DEEP Stop and utilizing Renesas unique low power sampling feature we can achieve excellent average power consumption.
For I/O reads at 50mS we expect less than 40uA
For UART/LIN and IO port scan evaluation we can expect around 200uA 90 60
Reference : F1L - Cyclic 50 ms
digital & analog IO scan.
40uA Target 30

23. Low Power Sampling Feature- DeepSTOP
CPU
VCC
VCC
Port Polling
Analog Polling
DPO
APO
Digital
switches
CNTR
CNTR
Analog
switches
yes
Port
ref
Range
Analog
Port polling block:
This allows to read a number of digital ports without CPU even being powered
A timer is set to periodically trigger a Port polling IP Block.
1.) Step is to turn on a dedicated Digital Output Port; this should be used to bias or turn on the digital switches so they can be read.
2.) A programmable counter is then used to allow or I/O settling. This can be programmed ~50uS -100uS
3.) After setting time then the the port I/O values are read
4.) The are compared against the I/O values at power down; if changed then you wake CPU to verify process the Change
Same process is available for Analog ports
AD results are compared against programmable AD thresholds values.
Wake
CPU?
COMPARE
COMPARE
Timer

24. Leading Edge of RL78 Low Power
Lower Power technology
CPU, Flash, System
Low Active power
As low as 66uA/MHz
Low standby power
0.49uA (STOP + 32kHz + RTC)
0.32uA (STOP + LVD)
Low power peripherals
LVD, RTC, WDT
Wake up from standby
19.1 usec
Long interval capability
0.5sec to 1 month
SNOOZE mode
ADC, UART/CSI(SPI)
No notes necessary

25. Low Power: Fully Configurable
Multiple Power Reducing Modes
Halt (DMA and all peripherals available)
Snooze (ADC, CSI/UART active)
STOP (RAM Retained)
The RL78 has a power management system that facilitates efficient use of power supply, critical for optimizing battery life.
In CPU Operating Mode the OCO (On-Chip-Oscillator) can be divided down to lower frequencies to save MCU current if maximum CPU performance is not required at the moment.
Changing over to HALT MODE can further reduce the MCU current drain, allowing Peripheral operation to continue, while suspending CPU instruction execution. In Halt Mode the High Speed system clocks can continue running ADC, timers, serial ports, etc, and the DMA can still operate to keep data transfers flowing between Peripherals and RAM without CPU intervention. HALT Mode can save as much as 80% of total MCU current compared to having the CPU running (example: 5.1mA current drain in RUN versus 1.1 mA in HALT Also, Halt mode can be entered from 32KHZ sub-clock CPU operation. When a processor Interrupt occurs during Halt mode, the CPU resumes operation in same CPU clock mode it was using before entering HALT, whether it was the High speed internal OCO, the High speed external oscillator, or the 32KHZ sub-clock.
STOP Mode achieves the lowest power consumption by turning off the High speed oscillator (internal OCO and external OSC), which means that peripherals requiring high speed clocks will also be disabled. However, the 32KHZ Sub-clock can still run in STOP Mode, enabling the operation of the Real-Time-Counter (RTC) for date and time, and the 12bit Interval Timer for timer events. Additionally, the internal Low speed OCO (15KHZ) can be used to clock the RTC and 12bit Interval timer as well. Also, the Low Voltage Detect, Watchdog timer and external interrupts can be enabled in STOP Mode. While in Stop Mode, any Timer interrupt or external interrupt which occurs, if enabled, can wake up the CPU to Operating mode.
Snooze Mode:
RL78 adds a special low power mode that didn’t exist on previous low power MCU generations, called the SNOOZE mode. If it is desired to have Serial Ports (SPI/CSI or UART) or ADC enabled, but suspended and waiting for incoming data while in STOP mode, the SNOOZE function can help reduce MCU current drain and be prepared for fast peripheral wake-up. The SNOOZE mode enables the Serial ports or ADC to start up with High Speed OCO clock operation from STOP mode, but without clocking the CPU, and therefore is similar to HALT mode, in that no CPU intervention is needed. The SNOOZE mode works in two ways, depending on the peripheral selected:
(a) For serial port (SPI/CSI and UART), the first clock edge of the UART Start bit or SPI clock line starts up the High speed internal OCO, and the serial port proceeds to receive data. Also, the high speed OCO is enabled. At this point the MCU has moved from STOP mode to SNOOZE Mode. If there is a serial error, the MCU reverts to STOP Mode and waits for the next data reception. If there is no data error, a serial interrupt is issued to the CPU, which causes a transfer to Operating Mode. In either case, power consumption is reduced by not powering the CPU until after data reception is complete. (b) For the ADC data conversion, a Timer trigger event from the RTC (Real-Time-Counter) or 12bit interval timer initiates a transition from STOP Mode to Snooze mode and an ADC conversion takes place. Since the CPU is not enabled, a current consumption savings of up to 68% can be obtained versus operating the ADC with CPU running. We can also selectively monitor external analog input values with the ADC in Snooze mode, to either store & evaluate those results, or if not in a certain range, we can ignore them and go back to STOP Mode. We’ll talk more about some additional ADC SNOOZE Mode operation advantages later.

26. Low Power: Snooze Mode Example (ADC)
ADC operation during standby state
4 comparison criteria: within/outside window, higher/lower than limit
Over 30% reduction in power vs. standard ADC operation
STOP
SNOOZE
Values in Range
Yes
ADC Value in range
Over 30%
reduction in power consumption No
ACTIVE
Process Data
SNOOZE Mode;
Conventional MCUs must be switched to CPU Operating mode to operate serial ports and ADC, at least minimally to initialize the peripheral setup and clocking. Then when data capture is complete the CPU must stay in Operating Mode and be interrupted to store and process the data.
Renesas RL78 SNOOZE Mode is an innovative feature created to reduce the dependency on the CPU for operating the serial and ADC peripherals while in Standby mode and thus reduce the corresponding MCU current drain overhead. Using the SNOOZE Mode setup, the serial ports or ADC can be ready in Standby, and a triggering interrupt can bring up the High speed OCO clock to operate the peripheral without CPU intervention. In this SNOOZE Mode example, the ADC conversion sequence is triggered by a periodic Timer interrupt event without the CPU. For ADC SNOOZE Mode, the ADC results are compared to an Upper limit or lower limit. There are 4 comparison modes that can result in an interrupt issued to wake the CPU:
“In Range” - Data matches to values within the Lower to Upper limit.
“Out-of-Range” - Data matches to values outside the Lower to Upper limit.
“Lower-than” - With the Upper Limit set to max ADC value, Data matches below the Lower Limit.
“Higher than” - With the Upper Limit set to max ADC value, Data matches above the Lower Limit
(With no data match the ADC goes back to STOP/Standby Mode waiting for another Timer trigger event)
When the timer trigger initiates an ADC conversion by turning on the High Speed clock, power consumption is conserved by only operating the Clock and ADC, not the CPU. After the ADC result is obtained, the comparison function determines if the result is of interest - whether it should be saved and evaluated further. In this example, an ADC result “Out-of-Range”, above the upper limit or below the lower limit causes an interrupt. The advantage of the SNOOZE mode is that it reduces the ADC Operation power consumption by >50% (1.8mA down to 0.8mA) in the example and only wakes up the CPU if the data is of interest - needing storage and analysis.
Timer Trigger
No Data Match
Timer Trigger
Data Match
Active mode
STOP mode
Snooze
STOP mode
Snooze
Active mode
ADC Data
ADC Data
mA if ADC Enabled
~800uA
~800uA
STOP mode 0.52uA
STOP mode 0.52uA

27. Flash Memory Challenges

28. Flash Requirements are Doubling Approximately Every Five Years
Flash Memory Trends
10M 8M 6M 4M 2M 1M
512K
256K
Body Control Modules
Engine Control Modules
Restraint Control Modules
Flash Requirements are Doubling
Approximately Every Five Years

29. World First 40nm Flash MCU for Automotive
320 MHz CPU
120 MHz Flash
~ 8 MByte
Lowest power consumption
Transistor / mm2
40nm
55nm
Other Option A
65nm
Other Option B
Previous generation
90nm
In the session XXC , RH850 & RL78 - Next Generation of Automotive Microcontrollers., Paul Kanan introduces this high level of the RH850 and RL78 MCU for the Automotive Market
<Click>  
 NOTE For Reviewer, the below notes are from the XXC presentation so you can better understand this slide
________________________________________________________________________________________________________________________________
What does this allow RENESAS
1.) 320MHz high end performance
2.) Low power
3.) More dies per wafer
100 80 60 40
Technology node
Leading Flash Process for Next Generation Automotive MCUs

30. Renesas Response to this Flash Growth
Current Product
Next Gen
V850/Fx4
RH850/F1x
256KB to 2MB
256KB to 8MB
V850/Px4
RH850/P1x
512KB to 2MB
512KB to 8MB
SH2A
RH850/E1x
1MB to 4MB
1MB to 8MB
78K0R/R8C
RL78/F1x
Up to 256K
Up to 512K

31. Advanced Networking and Security

32. Growth in In- Vehicle Networks
1000M
900M
800M
700M
600M
500M
400M
300M
200M
100M
50M
25M
# Nodes in Automotive
CAN **
CAN**
CAN* *
CAN
CAN
Key points on this slide
1.) Explosive growth Anticipated for LIN and Ethernet
2.) Consistent growth for CAN
3.) FlexRay… Slow growth predicted, bandwidth no longer main argument; only redundancy.
SA Data on slide is too generous… We see Flexray Flattening or moving down
4.) Ethernet is in favor of Automotive OEMS, see Ethernet as better network Backbone versus Flexray
5.) MOST is also losing favor at OEMs… We also see MOST usage decreasing in the future.
*2014 SA Data;
** REA estimate based on Market knowledge
Sources: Strategy Analytics, Automotive High Speed Bus Networks January 2012
Strategy Analytics, Automotive Network Protocol Demand Forecast

33. Renesas Response to this Network Growth
Current Product
Next Gen
Up to 12
up to 16 Ch
Up to 3 Ch
up to 5 Ch
Up to 3 Ch
Up to 3 Ch
Up to 6 Ch
Up to 7 Ch
CAN
Up to 3 Ch
Up to 3 Ch
Up to 2 Ch
Up to 4 Ch
1 Unit (2ch/Unit)
1 Unit (2ch/Unit)
1 Unit
1 or 2 Units
1 Unit
1 Unit
1 Ch
1 Ch
1 Ch
1 Ch
1 Ch
1 Ch

34. eliminate intermediate interrupts only 1 interrupt per message
LIN
Channels which support Master mode only
Dedicated H/W LIN peripheral
Detection of synch break, bus collision, timeout
Channels w/ Master mode and Slave mode
Master mode same s/w control architecture as above
Addition of Slave mode capability c
Break Field
Synch Field
ID 0
Data 1
Data n
Check Sum
LIN Bus
LMA interrupts
eliminate intermediate interrupts
only 1 interrupt per message

35. CAN CAN Channels with Flexible Message Buffer Structure
CAN2.0B Active standard ISO
Advanced message filtering capabilities
Flexible receive message buffers settings
up to 320 reception message buffer
16 transmit buffers per CAN Channel
Programmable Gateway routing for each channel
Automatic transfer block messages: 16  8
CAN time stamp output function
Advanced Message filtering capabilities – ( Up to 8 reception FIFO buffers)

36. FlexRayTM –Active Safety Examples
Inertial Sensor ECU
Brake ECU
Brake pedal ECU
Steering Angle ECU
Scalable Synchronous and asynchronous data transmission.
10 Mbit/sec/channel.
Deterministic data transmission
Fault tolerant with redundant transmission channels
Time trigger communication channels with global time base
Bus Guardian component supports error containment on the physical layer
Support both optical and electrical physical layers
Support multiple topologies (Star, linear, active, passive)
Here is an example of how FlexRay may be used..
1.) Inertial measurement unit.. Will send vehicle Yaw and acceleration data to the ESC stability control unit, which then is distributed to Brakes..… Flexray may be an ideal solution since this data is time critical.
Accelerator Opening
Pedal position
Wheel speed sensor/Slip data
Slip data
2.) Also, steering angle/control and brake pedal position data can be distributed over the FlexRay network.
 Steering Angle Position/control
 Accelerator Opening
Brake pedal position
Wheels speed sensor/ slip data
FlexRay bus Ch.A
FlexRay bus Ch.B

37. Security Concerns Increasing
How to protect my virtual dashboard design?
How to secure radio communications?
How to protect the odometer?
How to secure the remote entry system and the immobilizer?
How to protect against illegal tuning?
How to secure the car diagnosis?
Vehicle security awareness is increasing
OEMs are looking for better methods to protect against these types of attacks
Furthermore, another big concern from OEMs is some large scale attack … for example applying brakes to cause mass traffic jams
Toward a distributed in-vehicle security system

38. Two Emerging Standards for Security
Secure Hardware Extension (SHE): an low cost on-chip extension within a MCU which provides
A set of cryptographic services available to the application layer
Complete isolation of the secret keys and certificates from the rest of the MCU resources
SHE: released in April 2009 as a public specification endorsed by the German OEM consortium “HIS – Hersteller Initiative Software
EVITA (E-safety Vehicle Intrusion proTected Applications)
A collaborative research project with partial funding from the European Commission (EC).
The EVITA project defines the concept of a Hardware Security Module (HSM) incorporated into Automotive MCUs.
SHE
Provides the application layer with a fixed set of cryptographic services based on AES-128
Encryption & decryption
CMAC generation & verification
Random number generation
Boot loader verification
Unique device identification
Stores secret keys and certificates in a dedicated NVM not accessible by the application
The keys are referenced by an index (from 0 to 14)
Keys are updated in the secure memory with a specific procedure
EVITA A collaborative research project with partial funding from the European Commission (EC), with the following objectives
Define a powerful ECU security hardware extension that aims at designing, verifying, and prototyping an architecture for automotive on-board networks where security-relevant components are protected against tampering and sensitive data are protected against compromise
Prevent or at least detect malicious malfunction of in-vehicle e-safety applications
Detect manipulated information from external entities
Design and verify a ECU security architecture
ECU hardware security extension, software security components, corresponding (e-safety) security protocols
Implement, demonstrate and validate ECU security architecture for practicability
Evita sets classification for Automotive systems (Evita Low, Mid and High)
The EVITA HSM concepts breaks done into four components
A master-capable on-chip HW interface
A programmable intelligence (Secure CPU)
A set of dedicated cryptographic accelerators
A dedicated NVM area

39. Introducing Intelligent Cryptographic Unit (ICU)
Two ICU types coexist to address different application needs
ICU-S: slave unit offering symmetric cryptographic services
ICU-M: master unit offering asymmetric cryptographic services
Cryptographic Capabilities
“EVITA HSM” type-of IP
IP Complexity & Cost
Master unit
Private key cryptography
Public key cryptography
Dedicated CPU
ICU-M
“SHE” compliant IP
The Intelligent Cryptographic Unit ICU is Renesas response to security within the MCU.
This ICU is a peripheral within the MCU dedicated to allow OEMS to meet their security needs.
Slave unit
Private key cryptography
Control logic
ICU-S

40. Functional Safety

41. Functional Safety
In December 2011 ISO (International Standards Organization) release ISO26262.
This standard is the “adaption of IEC61508 to comply with needs specific to the application sector of electrical and/or electronic (E/E) systems within road vehicles
This standard provide normative guidelines on:
Automotive safety lifecycle (organization, development, production and EOL).
Assign specific Automotive Safety Integrity levels (ASIL) based on a risk based methodology
Based on ASIL level assign specific requirements to be met
Method on validating
Requirements for relations with suppliers

42. Renesas Standardized Development Process
Involvement of ISO26262 work products in Renesas standardized development process for MCU has been completed.
ISO26262 requirement for development process
Renesas internal
standardized
development
process
Assuming
requirement
Safety
analysis
Design
verification
work
Validation
ASIL D
Assumption of use
Assumed ASIL
FTA
FMEA
Independent
team review
safety
analysis
Simulation
/prototype
Validation with
assumed requirements
ASIL C
ASIL B
FMEA
Self review
ASIL A
Assumed
TSR
Safety analysis
report
Design verification
report
Verification report
Work product

43. Development Process for LSI (SEooC)
Safety goal
Safety assessment
System verification
(OEM/Tier1)
and validation
Functional safety concept,
(FSR, preliminary architectural assumption)
Safety validation
Requirement derivation
and design for system
(OEM/Tier1)
Technical safety concept,
(TSR, System design)
Item Integration
Validation for the system
Decision for ASSP
Device safety plan
Device safety assessment
Device safety concept
(Assumed device TSR/HSRS, device design, Assumptions related to the design external to device)
Device testing
Renesas will apply a tailored MCU SEooC lifecycle.
Concrete safety goals are not applicable to an MCU SEooC as they are defined on item level.
The ISO process requirements will be carried out according to designated ASIL level
Renesas will implement the HW diagnostic measures as agreed within discussion of customers and IP developed.
The overall metrics for ASIL (A,B,C,D) have to be achieved by a combination of MCU HW and user SW measures.
Renesas is open to jointly agreed on the interfaces and the required work products.
Requirement derivation
and design for device
(device vendor)
Product verification
(MCU vendor)
and validation
Device safety verification
(Verification of consistency and completeness between requirement and design)

44. Platform Functional Safety Features
Example of features available or under consideration
ASIL C/D
ASIL A/B
Redundant Core Lockstep
Error Management
Logic / Memory BIST
ECC on memories
Clock Monitors
Memory Patrol
POF / LVI
MPU, Timing Supervision,
Peripheral Diag./protection
ADC, CSI/UART loopback
… (t.b.d.) QM
ECC on memories
Clock Monitors
Error Management
Software self tests
POC / LVI
MPU
Peripheral Diagnostics
ADC, CSI/UART loopback
ext./int. intelligent WDT
ECC on memories
Clock Monitors
POC / LVI
MPU, PPU
Peripheral Diagnostics
ADC, CSI/UART loopback
… (t.b.d.)
Examples of some functional safety features (hardware and software) available for use in our products.
AUTOSAR ASIL D
Compiler ASIL D
Tools
SW CST
SW ROM / RAM test
SW Peripheral Tests
AUTOSAR ASIL B
Compiler ASIL B
Tools

45. Roadmaps

46. RH850F1x for Body 1. Extreme Low Power consumption
Integrated
MCU
1. Extreme Low Power consumption
Low power operation at 0.5mA/MHz at single core
Dual core for High-end for low power & performance
Enlarge battery life time in standby mode
2. Full coverage of Body Networking
New Gen
Gen.4
Gen.2 / Gen.3
CAN/LIN
Flex Ray
Ethernet
CAN/LIN
Flex Ray
CAN/LIN
Ethernet
3. Hardware Security module
Hardware Security Support to meet “SHE” (Secure Hardware Extension)
and Evita concept. Standardization in HIS consortium
4. Wide Line-up to cover various body systems
Memory range :128KB to 8MB Flash memory
Package range : 48pin to 357pin

47. CAN RL78/F1x for Body 1. Extreme Low Power consumption
Integrated
MCU
1. Extreme Low Power consumption
Low power operation at 130uA/MHz at single core
Special Snooze mode or Cyclic power applicatoins
2. Ideal for LIN Slave and single / dual CAN
CAN
3. High Temperature support for Engine Compartment
Support for 150° C Ambient condition
4. Wide Line-up to cover various body systems
Memory range :8KB to 512KB Flash memory
Package range : 20pin to 144pin

48. MCU Roadmap for Body RH850/F1x RL78/Fxx V850/Fx4-H V850/Fx4 V850/
　 　　　 　　　
Gateway
RH850/F1x
V850/Fx4-H
V850/Fx4
V850/
CAG4-M
MHz
256KB - 8MB
1 - 6 CAN
FlexRay / Ethernet
BCM
Stand Alone ECU
V850/
Fx3
V850/Fx4-L
MHz
64KB - 2MB
1 - 6 CAN
V850/
Fx3-L
R32C
M16C
Dedicated ECU
78K0/
Fx2&Kx2
78K0R/
Fx3
RL78/Fxx
MHz KB
0 - 2 CAN
M16C
R8C/2x
R8C/3x
R8C/5x
78K0/Fx2-L
78K0S/Kx1+

49. RH850P1x/R1x for Chassis & Safety
ASIL D capable
Lock step dual core (LSDC) for ASIL-D
functional safety requirement
Scalable LSDC line up for Chassis & Safety
applications (240MHz to 80MHz )
Safety mechanism to reduce software and
system overhead
RENESAS Expertise
Functional Safety
Standardisation
Activities
- IEC61508
- ISO26262
Enough experience
of functional safety
ASIL B capable
Work products
Required for LSI
Cost conscious solution for ASIL-B
functional safety requirement
Single core with hardware measures &
software core self test
Combining RH850 R1x + System base
chip to realize ASIL-D capable system
Support and
Solutions for
Effective development

50. MCU Roadmap for Chassis & Safety
LSDC: Lock step dual core
　MP Start 　　　 　　　
LSDC
Integrated Safety Unit
High End Chassis controller
MHz / 2-4MB
RH850/P1x
Ultra-High
240MHz
LSDC x 2
Stability Control
High EPS
MHz
/1M-2MB
V850/Px4
1MB LSDC
240MHz, LSDC+PCU
RH850/P1x
High-End
V850 / PHO3
1MB
SH7227-1MB
LSDC
SH7147
512KB
SH7227
512KB LSDC
RH850/P1x
Mid-Range
EPS/Braking
160MHz
/512K -1MB
V850/Px4
512KB LSDC
V850/PG2
128KB
V850/Px4-L
512KB LSDC
80/160MHz, LSDC
SH72A0/A2
512KB
LSDC
RH850/P1x
Mid-Low
H8SX/1720S
512KB
ABS/
Airbag
80MHz /256KB-512KB
V850/Rx3
80MHz, LSDC
H8SX/1725
256KB
V850/Fx4-L
RH850/R1x
V850/Fx4
80MHz,
Single Core
V850/Fx3

51. RH850E1x for Power train System
1. High Performance & Safety
4 CPUs ( Dual CPU Core / Lock Step Dual
/ Peripheral CPU )
320MHz Main CPU operation
ASIL-D capable for Functional Safety with
Lock Step Dual
2. Dedicated Hardware for Power train
Advanced Timer Unit
Autonomous Pulse Adaptor (APA) for Direct Injection
Digital Filter Engine (DFE) for knock detection
 Analog Digital Convertor
3. Scalability for downsizing
Software compatibility from High-end to Low-end
High-end at 320MHz/8MB flash to Low-end at 80MHz/ 1MB flash
4. High temperature operation
Tj = 170 degC max. (KGD)

52. MCU Roadmap for Power train
　 　　　 　　　
40nm
RH850/E1x
240~320MHz x2core
8MB Flash
~240MHz x2core
4MB Flash
160MHz
2MB Flash
80MHz
1MB Flash
> 240MHz
> 4MB
SH72567R
200MHz
4MB
~ 200MHz
~ 4MB
SH72546R
200MHz
3.75MB
SH72544R
200MHz
2.5MB
SH72533
160MHz
2MB
~ 160MHz
~ 2MB
SH72543R
200MHz
2MB
SH7059
80MHz
1.5MB
SH72531
120MHz
1.25MB
SH7058S
80MHz
1MB
V850/GP4
80MHz
1MB
~ 80MHz
~ 1MB
V850/GP8
80MHz
512kB 52 52 52

53. Next Gen. MCU for HEV/EV 1. High Performance & Safety
3 CPUs (Lock Step Dual / Peripheral CPU )
240MHz Main CPU operation
ASIL-D capable for Functional Safety with
Lock Step Dual
2. Dedicated Hardware for Motor Control
- Cost effective built-in Resolver Digital Converter
(collaboration with Tamagawa-Seiki)
Less CPU load Built-in Enhanced Motor Control Timers
2 motor controllable by 1 MCU
3. Scalability for downsizing
Software compatibility from High-end to Low-end
High-end up to 240MHz/4MB Flash
4. Wide Line-up to cover various HEV/EV systems
Motor / Generator, DC/DC, Vehicle control & Battery management

54. MCU Roadmap for HEV/EV RH850/C1x 2RDC-IF, 4MB, 320MHz, LSDC+1CPU+PCU
　 　　　 　　　
MG (Motor Generator)
RH850/C1x
2RDC-IF,
4MB, 320MHz,
LSDC+1CPU+PCU
RH850/x1x
1RDC-IF,
2MB, 240MHz,
LSDC+PCU
V850/Px4-E
1MB,LSDC,RDC-IF
SH7227-1MB
LSDC
SH72AW
RDC-IF
V850/Px4
512/384KB, LSDC
V850/PG2
240/496KB
SH72A2
-512KB
SH7147
DC/DC
V850/Fx4-Motor
RH850/P1x
V850/Fx3
SH72A0
-512KB
Vehicle Control
V850/Fx4-H
V850/FK4-G
V850/Fx4
RH850/F1x
Battery Management
V850/Fx3 54

55. Questions?

56. ‘Enabling The Smart Society’
Challenge: “How to meet the next generation of automotive MCU real time control requirements while at the same time meeting green requirements and “Smart Car” vehicle evolutions which OEMs and consumer are demanding.
Solution:
“Renesas’ next generation RL78 and RH850 Automotive MCU for real time embedded control will meet the demands of advanced vehicle architectures and support the “smart society” consumer demands.
Do you agree that we accomplished the above statement?