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Dirk Beernaert, European Commission Brussels, 16 December 2010 IC design Challenges and opportunities Workshop.

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Presentation on theme: "Dirk Beernaert, European Commission Brussels, 16 December 2010 IC design Challenges and opportunities Workshop."— Presentation transcript:

1 Dirk Beernaert, European Commission Brussels, 16 December 2010 IC design Challenges and opportunities Workshop

2 Semiconductors as key enabling industry Electronics WW$1500B / Europa $315B Automotive Industrial Defense Medical Space Semiconductors $256B / Europa $41B Service Providers WW$6300B / Europa $1600B 2007 World GDP=65200BUS$ (ppp based) - Internet Services Providers - Games - Broadcast - Telecom Operators Semiconductors provide the knowledge & technologies that generate some 10% of global GDP. Source: IMF, ESIA, WSTS, Decision

3 The Supply Chain Today Automotive Industrial and Medical Military, Civil Aerospace, Security Consumer Communications Data Processing

4 The evolving SC value chain / landscape Academia, Scientific Research Institu- tions Eq.& Materials IDM DISTI (branded) OEM Service providers (virtual) Network op. (Consumer) Retail Businesses, Consumers, Authorities From a linear chain... S/C Mfg Services: Foundry SATS Fabless IP Providers: IP blocks Software (firmware, stacks, middleware, OS ) Design houses EDA DISTI ODM EMS (branded) OEM Module makers Service providers/ (virtual) network op. (Consumer) Retail Distrib. Content Industry: Providers Aggregators Service prov. Businesses, Consumers, Authorities Academia, Scientific Research Institu- tions Eq.& Materials IDM Logistics service providers... to a networked model Source: ESIA

5 Global Consolidation: Number of Logic IDMs with Fabs. European Chip makers are moving up the value chain: From the hardware supply side into the final application IBS 2009, ST 2010 Semi equipment Semi materials Wafer foundry Software System mgmt Chip maker Application Content protection Infrastructure System integrator Service provider Content provider Delivery network Gateway mgmt Legislator regulations Changing business models

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7 - Keep research, manufacturing, integration & system competence in Europe? IP, lead markets, user-supplier relationships, regional innovation clusters, equipment, manufacturing, SMEs Policy & more efforts to keep Europe attractive for investments in semiconductor research & manufacturing and for their application in key lead markets High on EU 2020 Agenda Nanoelectronics Small, smaller, smarter

8 - Advanced communication & computing components enabling pervasive applications - Lower cost, higher performance and more functionality performance Smart design and Smart manufacturing of Smart Components Enabled by Power consumption - Moores Law: Miniaturization Baseline CMOS: CPU, Memory, Logic 130nm 90nm 65nm 45nm 32nm 22nm Beyond Moore Analog/RFPassivesHV Power Sensors Actuators Biochips Information Processing Digital content SoC Interacting with people and environment Non-digital SoC & SiP Combining SoC and SiP: Higher Value Systems More than Moore: Diversification Digital Society

9 Current FP7 R&D Work Programme To stimulate interaction of system and technology to better explore European system competences. To address energy efficiency needs for mobile applications Nanoelectronics products as system enablers and solution providers for global challenges as aging society, global warming, growing population or sustainable manufacturing. To prepare for beyond traditional shrinking (ITRS roadmap) - Moores Law: Miniaturization Baseline CMOS: CPU, Memory, Logic 130nm 90nm 65nm 45nm 32nm 22nm Beyond Moore Analog/RFPassivesHV Power Sensors Actuators Biochips Information Processing Digital content SoC Interacting with people and environment Non-digital SoC & SiP Combining SoC and SiP: Higher Value Systems More than Moore: Diversification

10 Manufacturing, Equipment assessment and Access –Access to nano-manufacturing and to advanced technologies to be assured in Europe. –Access to world wide equipment market for European suppliers, especially SMEs, need to be stimulated. –Access to design tools and multi-project wafers fabrication for education, PhD and SMEs. Semiconductor Equipment for Wafer Bonding with Plasma Activation EV Group, CEA-LETI, Soitec 3D Integration of Bulk Si Wafers EV Group, CEA-LETI, STMicroelectronics Crolles II Low Energy and Dose Implant Test SEMILAB, Fraunhofer IISB, ST Microelectronics Crolles II, NXP Crolles R&D Ruthenium Atomic Vapor Deposition Competitiveness in Nanoelectronic Device Generations AIXTRON, Fraunhofer IISB, Infineon Munich Metrology Using X-Ray Techniques Jordan Valley, CEA-LETI, STMicroelectronics Crolles II, NXP Crolles R&D

11 ENIAC Joint Undertaking as Public-Private Partnership Industry and R&D actors Commission and Public Authorities Executive Dir. and secretariat Health & the Aging Society Energy Efficiency Safety & Security Automotive & Transport Communication & Digital Lifestyles Design Technologies Equipment, Materials & Manufacturing Semiconductor Process & Integration New emphasis

12 FP7-CIP/ICT/ENIAC Budget Profiles: 70% increase in period 2011-13 M 2007200820092010201120122013TOTAL PF7 ICT1.1891.2171.2271.2411.3821.5821.7609.597 CIP 5852105113120135149732 ENIAC JU (2/3natl + 1/3EC) 97106871252406201275

13 Whats next for nanoelectronics R&D in Europe? What are the challenges ahead in a globalized world? What are the priorities? How to measure impact and success? Whats necessary to better exploit results in Europe? Whats necessary to innovate and invest in Europe? Whats next for nanoelectronics R&D in Europe?


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