1. CMP 301A Computer Architecture 1 Lecture 4

2. 2 Outline zISA Introduction zISA Classes yStack yAccumulator yRegister memory yRegister register/load store yMemory memory

3. 3 Introduction - Instruction Set Architecture instruction set software hardware

4. 4 ISA Classes ISA Classes? zStack zAccumulator zRegister memory zRegister register/load store zMemory memory Operation Input1Input2 Output

5. 5 ISA Classes: Stack Operate on TOS, put result TOS C= A+B? PUSH A PUSH B ADD POP C Operation TOP OF STACK MEMORY

6. 6 ISA Classes: Accumulator Accumulator : Implicit input & output. C= A+B? LOAD A - Put A in Accumulator ADD B - Add B with AC put result in AC STORE C- Put AC in C Operation Accumulator (AC) MEMORY

7. 7 ISA Classes: Register-Memory Input, Output: Register or Memory C= A+B? LOAD R1, A ADD R3, R1, B STORE C, R3 Operation Register File MEMORY

8. 8 ISA Classes: Register-Register LOAD/STORE ARCH. C= A+B? LOAD R1, A LOAD R2, B ADD R3, R1, R2 STORE C, R3 Operation Register File MEMORY

9. 9 ISA Classes: Memory-Memory Input, Output: Memory C= A+B? ADD C, A, B Operation MEMORY

10. 10 Pros/Cons of ° Register–register: 0 memory operands/instr, 3 (register) operands/instr + Simple, fixed-length instruction encoding. Simple code generation model. Instructions take similar numbers of clocks to execute –Higher instruction count than architectures with memory references in instructions. Some instructions are short and bit encoding may be wasteful. ° Register–memory +Data can be accessed without loading first. Instruction format tends to be easy to encode and yields good density. –Operands are not equivalent since a source operand in a binary operation is destroyed. Encoding a register number and a memory Address in each instruction may restrict the number of registers. Clocks per instruction varies by operand location. ° Memory–memory +Most compact. Doesn’t waste registers for temporaries. –Large variation in instruction size, especially for three-operand instructions. Also, large variation in work per instruction. Memory accesses create memory bottleneck.

11. 11 General Purpose Registers Dominate

12. 12 Review Question Consider the following two models: Memory-Memory (three operand, memory based) - All three operands of an instruction are in main memory. Load-Store (three operand, register based) - All operations work on the 16 registers. There is no restriction on which register can be used as operand or result. To make the memory efficiency measurable, use the following assumptions for both instruction sets: The opcode is always 1 byte (8 bits) long. _ All memory addresses are 2 bytes (16 bits) long. _ All data operands are 4 byte (32 bits) long. _ The total instruction length is a multiple of a byte. A = B + C*D; B = A + C*E; Count the number of instruction bytes that need to be fetched, as well as the number of data bytes transferred. Which model is the most efficient one in respect to the code size? Which one needs the least memory bandwidth (sum of the instruction and data transfers)?