Presentation on theme: "CMOS Technology Why CMOS Qualitative MOSFET model Building a MOSFET"— Presentation transcript:
1 CMOS Technology Why CMOS Qualitative MOSFET model Building a MOSFET CMOS logic gatesHandouts: Lecture Slides
2 Building Bits from Atoms We Need Three Things:Represent and communicate bitsTransform bits (Invert, AND, OR,…)Remember bits (storage)…subject to the fundamentals of physics:Uncertainty, Noise, c, Thermodynamics,…
3 Wish ListSmall, simple, repeatable and stable non-linear devices with gain using readily-available materialsCan mass produce very large quantities of devices and wiresConsistently improves performance and density (scales) with ongoing R&D investment
4 Wishes FulfilledSmall, simple, repeatable and stable non-linear devices with gain using readily-available materialsSilicon + Aluminum/Copper + …Can mass produce very large quantities of devices and wiresLiterally print billions at a timeConsistently improves performance and density (scales) with ongoing R&D investmentMoore’s Law: 2x density every 1.5 to 2 years≈ $1T in cumulative investment
5 MOSFETS: Gain & non-linearity MOSFETs (metal-oxide-semiconductor field-effect transistors) are four-terminal voltage-controlled switches. Current flows between the diffusion terminals if the voltage on the gate terminal is large enough to create a conducting “channel”, otherwise the mosfet is off and the diffusion terminals are not connected.Why are MOS devices King?
6 FETs as switchesThe four terminals of a Field Effect Transistor (gate, source, drain and bulk)connect to conducting surfaces that generate a complicated set of electricfields in the channel region which depend on the relative voltages of eachterminal.CONDUCTION:If a channel exists, a horizontal field willcause a drift current from the drain tothe source.INVERSION:A sufficiently strong vertical field willattract enough electrons to the surface tocreate a conducting n-type channelbetween the source and drain.
7 “Linear” operating region Larger VDS increases drift current butalso reduces vertical field componentwhich in turn makes channel less deep.At some point, electrons are traveling asfast as possible through the channel(“velocity saturation”) and the currentstops growing linearly.
8 Saturated operating region This looks just like a fet with a channellength of L’ < L. Shorter L’ impliesgreater IDS. As VDS increases, δL getslarger.When VDS = VGS-VTH the vertical fieldcomponent is reduced and the channel ispinched-off. Electrons just keep travelingacross depletion region…
10 FETs come in two flavors By embedding p-type source and drain in a n-type substrate, we can fabricate acomplement to the N-FET:The use of both NFETs and PFETs – complimentary transistor types – is a keyto CMOS (complementary MOS) logic families.
13 CMOS Inverter VTC When both fets are saturated, small changes in Vin produce large changes in Vout
14 Think Switches pullup: make this connection when VIN near 0 so that VOUT = VDDpulldown: make this connectionwhen VIN near VDD so that VOUT = 0
15 Let’s build a MOSFETStart with a 500μ slice of a silicon ingot that has been doped with an acceptor(typically boron) to increase the concentration of holes to 1014/cm /cm3. Atroom temperature, all the dopants in this p-type material are ionized, turning thesilicon into a semiconductor.We’ll build many copies of the same circuit onto a single wafer. Only a certainpercentage of the chips will work; those that work will run at different speeds.The yield decreases as the size of the chips increases and the feature sizedecreases.Wafers are processed by automated fabrication lines. To minimize the chanceof contaminants ruining a process step, great care is taken to maintain ameticulously clean environment. So put on your bunny suits and let’s begin…
16 Creating patterns on the wafer A “thick” (0.4u) layer of SiO2 is formed by oxidizing the surface of the waferwith wet oxygen (we rust it!). The SiO2 will serve as insulation between theconductive substrate and subsequent conductive layers we’ll build on top ofthe oxide.Now we’ll form a pattern in the SiO2 using a mask & etch process. First thewafer is coated with a layer of photoresist. Photoresist becomes solublewhen exposed to ultraviolet light…Using a mask to protect parts of the wafer, we’ll expose those portions ofthe wafer where we want to remove the photoresist. We’ll use differentmasks when creating each of the different structures on the wafer.
17 The etching processThe exposed photoresist is removed with a solvent. The unexposedphotoresist remains, masking portions of the underlying SiO2 layer.A chemical etch is then used to remove the revealed silicon dioxide.Finally, the remaining photoresist is removed with a different solvent andwe’re left with pattern of insulating SiO2 on top of exposed p-typesubstrate.
18 Gate oxide & polysilicon Now a “thin” (20 A) layer of SiO2, called gate oxide, is grown on the surface. Thegate oxide needs to be of high quality: uniform thickness, no defects! The thinnerthe oxide, the more oomph the FET will have (we’ll see why soon) but the harder itis to make it defect-free. Coming soon to a fab near you: 12 A gate oxide...On top of the thin oxide a 0.7u thick layer of polycrystalline silicon, calledpolysilicon or poly for short, is deposited by CVD. The poly layer is patterned andplasma etched (thin ox not covered by poly is etched away too!) exposing thesurface where the source and drain junctions will be formed. Poly has a high sheetresistance of 20 Ω/sq which can be reduced by adding a layer of a silicidedrefractory metal such titanium (TiSi2), tantalum (TaSi2) or molybdenum (MoSi2)=> 1, 3 or 5 Ω/sq.
19 Source/drain diffusions Donor implants are used to create self-aligned MOSFET source/draindiffusions and substrate contacts. Usually As is preferred to obtain shallowN-type diffusions and minimal lateral diffusion. High doses are needed tomake low resistance (25 Ω/sq) diffusion wires. Afterwards a short thermalannealing step is performed to repair surface damage caused by theimplantation.This completes the construction of the MOSFET itself. Now we’ll add themetal wiring layers…
20 Wires: metal interconnect After a layer of SiO2 insulation has been deposited, aluminum orcopper is deposited, patterned, then etched to form low-resistance(.07 Ω/sq) interconnect. With planarization of the SiO2 (a mechanicalpolishing step that creates a flat surface), multiple levels of metalinterconnect are possible -- 3 to 6 layers are common in today’sprocesses.
21 Standard Cell Layout for Inverter Physical design of a CMOS gate is represented by a mask layout showingwhere material on each layer (ndiff, pdiff, poly, m1, m2, …) should be placedon the silicon wafer. Each manufacturing process has a set of design rulesthat determine minimum widths, spacings, overlaps, etc.
22 Beyond Inverters: Complementary pullups and pulldowns We want complementary pullup and pulldown logic, i.e., thepulldown should be “on” when the pullup is “off” and viceversa.Since there’s plenty of capacitance on the output node, when theoutput becomes disconnected it “remembers” its previous voltage -- atleast for a while. The “memory” is the load capacitor’s charge. Leakagecurrents will cause eventual decay of the charge (that’s why DRAMsneed to be refreshed!).
26 General CMOS gate recipe Step 1. Figure out pulldown network thatdoes what you want, e.g., F = A*(B+C)(What combination of inputs generates alow output)Step 2. Walk the hierarchy replacing nfetswith pfets, series subnets with parallelsubnets, and parallel subnets with seriessubnetsStep 3. Combine pfet pullup networkfrom Step 2 with nfet pulldown networkfrom Step 1 to form fully-complementary CMOS gate.
27 Emerging Big Issue: Power Energy dissipated = C VDD2 per gatePower consumed = f n C VDD2 per chipWhere f = frequency of charge/dischargen = number of gates /chip
28 Unfortunately… Modern chip (UltraSparc III, Power4, Itanium 2) dissipates from 80W to 150W with a Vdd ≈ 1.2V(Power supply current chip is ≈ 100 Amps)Ampacity is similar to a big double oven!Cooling challenge is like making the filament of a100W incandescent lamp cool to the touch!Worse yet…Little room left to reduce VddnC and f continue to grow
29 Emerging Big Issue: Wires Today (i.e., 100nm):τRC ≈ 50ps/mmImplies 2ns to traverse a 20mm x 20mm chipThis is a long time in a 2GHz processor
30 Summary MOSFET features CMOS features PN junctions provide electrical isolationSwitch-like behavior controlled by VGSShrinking geometries improves performanceCMOS featuresCMOS logic is “naturally” inverting: “1” inputs lead to “0” outputsGood noise margins becauseVOL = 0, VOH = VDDcomplementary logic has high gainNo static power dissipationNext time: timing, converting functionality to logic