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INTEL CONFIDENTIAL 1 Intel Corporation Platform Engineering Group Nick Klein Jan 30, 2014 The PFIT Project WW07'14.

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Presentation on theme: "INTEL CONFIDENTIAL 1 Intel Corporation Platform Engineering Group Nick Klein Jan 30, 2014 The PFIT Project WW07'14."— Presentation transcript:

1 INTEL CONFIDENTIAL 1 Intel Corporation Platform Engineering Group Nick Klein Jan 30, 2014 The PFIT Project WW07'14

2 2 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 The PFIT Project Agenda Objective Strategy Timeline

3 3 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 The PFIT Project key objectives Apply LEAN principles to Advanced FI Define equipment required to optimize automated Advanced FI test throughput time (TPT) Development of industry standard automated Advanced FI equipment to significantly reduce FI throughput time and expense.

4 4 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 Reasons for the PFIT project Advanced FI methodologies currently rely on equipment intended for functional FI. Functional and Advanced FI equipment needs differ significantly, in that testing is often performed on completely non-functional parts, and require much higher test currents and dual-polarity voltages. This project extends the capability of Advanced FI across all product lines to significantly decrease TPT.

5 5 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 The PFIT Project Agenda Objective Strategy Timeline

6 6 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 The PFIT Project strategy Identify strategies to enhance existing functional FI Determine essential minimum equipment Curve tracing Latch up High-current Bin8 Develop TIU Universal carrier interface Daughter board per product Develop automated LabView test procedures Mostly universal across product lines Document entire system for copy-exact to other sites

7 7 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 The PFIT Project Agenda Objective Strategy Timeline

8 8 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 The PFIT Project timeline Spec writing Board design and Software Design Harness Design Boards in house Pre-Power On testing. Validation Phase 2Phase 1Completion Demos and implementation

9 9 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0

10 10 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 Back up

11 11 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 Backplane block diagram

12 12 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXXIntel ConfidentialRevision: 1.0 Family board block diagram


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