1. © H. Heck 2008Section 1.11 Module 1Introduction Topic 1Overview OGI EE564 Howard Heck I1I1 V1V1 I2I2 V2V2 dz

2. Course Overview EE 564 © H. Heck 2008 Section 1.12 Contents What is an interconnect? Administrative (text, grading, etc.) Syllabus & Schedule Expectations Weekly Feedback Assignment Additional References

3. Course Overview EE 564 © H. Heck 2008 Section 1.13 What is an Interconnect? H E V I D CLK D

4. Course Overview EE 564 © H. Heck 2008 Section 1.14 Administrative Information CourseECE564High Speed Digital Interconnect ObjectiveYou will learn to analyze and design inter-chip interconnect circuits for high speed digital applications. Upon completing the course, you will possess the necessary skills to implement designs operating from several hundred MHz to a few GHz. InstructorHoward Heckhoward.heck@intel.com503-264-7831 Text S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1 st edition, ISBN 0-471-36090-2. Grading20% 20% 25% 25% 10% 4 Homework Sets Midterm Final Project Weekly Feedback Office HoursBy Arrangement

5. Course Overview EE 564 © H. Heck 2008 Section 1.15 Course Outline 1.Introduction 1.Overview 2.Trends & Challenges 3.Interconnect Technology Overview 2.Transmission Line Basics 1.Transmission Line Theory 2.Basic I/O Circuits 3.Reflections 4.Parasitics & Loading 5.Modeling, Simulation, & Spice 6.Measurement: Basic Equipment 7.Measurement: Time Domain Reflectometry 3.Analysis Techniques 1.Lattice Diagrams 2.Bergeron Diagrams

6. Course Overview EE 564 © H. Heck 2008 Section 1.16 Course Outline #2 4.Metrics & Methodology 1.Synchronous Timing 2.Signal Quality 3.Source Synchronous Timing 4.Derived Clock Timing 5.Design Methodology 5.Advanced Transmission Lines 1.Losses 2.Intersymbol Interference (ISI) 3.Crosstalk 4.Frequency Domain Analysis 5.2 Port Networks & S-Parameters

7. Course Overview EE 564 © H. Heck 2008 Section 1.17 Course Outline #2 6.Multi-Gb/s Signaling 1.Projections, Limits, & Barriers 2.Differential Signaling 3.Equalization 4.Modulation 7.Special Topics (will cover as time permits) 1.Diode Clamping 2.Termination Techniques 3.Topology Trade-offs 4.Advanced I/O Design 5.Ground Bounce 6.Non-Ideal Return Paths

8. Course Overview EE 564 © H. Heck 2008 Section 1.18 Schedule ClassTopic(s)Key ConceptsReadingProblems 11-1, 1-2, 1-3, 2-1 Transmission line impedance & velocityChapters 1 & 7 Set #1 Due [5] 22-2, 2-3 Load lines, simple I/O models, and reflectionsChapter 2 Appendix A 32-4, 2-5 Capacitance & inductance effects Spice. 42-6, 2-7 Time domain reflectometryChapter 11 (except 11.8) 53-1, 3-2 Lattice & Bergeron diagramsMotorola AN 1406 Set #2 Due [9] 64-1, 4-2, 4-3 Synchronous timing analysis, signal quality metrics, & source synchronous timings Chapter 8.1 Chapter 9.2 74-4, 4-5 Derived clock timings & Modern design methodology Chapter 8.2 Chapter 9 85-1, 5-2 Conductor & dielectric losses Intersymbol interference Chapter 4.1 Appendix C Chapter 4.4 Set #3 Due [12] 95-4 Reflection coefficient, input impedance, load impedance 105-5 Vector network analyzer, S- parameters, ABCD parameters Chapter 11.8

9. Course Overview EE 564 © H. Heck 2008 Section 1.19 Schedule #2 DateTopicExpectationReadingProblems 105-5 Vector network analyzer, S- parameters, ABCD parameters Chapter 11.8 11Midterm 6-3 1 hour, open book exam Equalization techniques Set #4 Due [15] 126-1 Shannon’s limit, SNRChapter 6 Project Due 3/24 136-2 Differential signaling 146-4 Modulation techniques 155-3 Even/odd mode impedance & velocity, near/far end noise. Chapter 3 16 Review/Special topics 17 Review/Special topics 18 Final Exam Due 19 Project Due 20

10. Course Overview EE 564 © H. Heck 2008 Section 1.110 Expectations What to expect from me: Effort to convey the subject matter as clearly as possible. To use your feedback clarify the material where needed. Emphasis on application with real world examples. Basics plus contemporary & future issues. Homework problems that reinforce and expand the lecture material. To teach you enough that you could execute the design of a high speed interconnect.

11. Course Overview EE 564 © H. Heck 2008 Section 1.111 Expectations What I expect from you Prompt attendance. We’ll start on time. Effort. The only way to get a poor grade is to demonstrate poor effort. You will help yourself if you study the lecture notes prior to the class in which they are covered.  I will warn you in advance of specific topics, descriptions, derivations, etc. that I expect you to learn on your own.  By doing this, we’ll get to cover the advanced material that should be part of a graduate level class. Feedback. During class & as part of a weekly assignment.

12. Course Overview EE 564 © H. Heck 2008 Section 1.112 Weekly Feedback Assignment Due each Monday at 8 a.m. Send to my e-mail address. Content: 1.What was the most useful thing (for the week or in each lecture) that was covered in the lecture(s)? 2.What was the concept (week or per lecture) that needed further explanation or clarification?

13. Course Overview EE 564 © H. Heck 2008 Section 1.113 Additional References S. Hall & H. Heck, Advanced Signal Integrity for High Speed Digital Designs, John Wiley & Sons, to be published in 2009. W. Dally & J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998, 1 st edition, ISBN 0-521-59292-5. (This is the textbook we used in 2000.) H. Johnson and M. Graham, High-Speed Signal Propagation: Advanced Black Magic, Prentice Hall, 2003, 1 st edition. R.E. Matick, Transmission Lines for Digital and Communication Networks, IEEE Press, New York, 1995, ISBN 0-7803-1121-3. (Classic text on transmission lines.) Ramo, Whinnery, and Van Duzer, Fields and Waves in Communication Electronics, John Wiley & Sons, New York, 2 nd edition, 1985, ISBN 0-471-871130-3. B. Young, Digital Signal Integrity, Prentice-Hall PTR, 2001, 1 st edition, ISBN 0-13-028904-3. R. Poon, Computer Circuits Electrical Design, Prentice Hall, Englewood Cliffs, NJ, 1995, ISBN 0-13-213471-3. (This is the textbook we used in 1999). H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990, ISBN 0-201-060080-6.

14. Course Overview EE 564 © H. Heck 2008 Section 1.114 Additional References #2 D. Derickson & M. Muller (ed.), Digital Communications Test and Measurement, Prentice Hall, 2008, ISBN-13;978-0-13-220910-6. M. Li, Jitter, Noise and Signal Integrity at High-Speed, Prentice Hall, 2008. H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, Prentice Hall PTR, Englewood Cliffs, NJ, 1993, ISBN 0-13-395724-1. W.R. Blood, MECL System Design Handbook, Motorola, Inc., 4 th edition, 1988. S. Dabral and T. Maloney, Basic ESD and I/O Design, Wiley Interscience, New York, 1998, ISBN 0-471-25359-6. P. Magnusson, G. Alexander, V. Tripathi, Transmission Lines and Wave Propagation, 3 rd edition, CRC Press, 1992, ISBN 0-8493-4279-1. Throughout the class I will reference additional papers in the material for each section.