Proposed TAM for AMBA-based SOC The main contribution of our technique is to reuse the on/off chip bus bridge as a test interface during the test mode. The AHB master component on the bridge is reused as an interface between the ATE and the chip under test, and then, the ATE acts as a virtual bus master. By utilizing the functional buses as dedicated test paths and eliminating the bus-direction turnaround delays. In this paper, the bridge with the test controllability is referred to as a test-ready bridge.
Project Midterm project AHB bus Final project Hybrid Test Interface Controller
Schedule DateProgressDateProgress 10/25Propose paper12/06Implement final project 11/01Implement midterm project12/13Implement final project 11/08Simulation12/20Simulation 11/15Implement final project12/27Test final project 11/22Implement final project01/03Test final project 11/29Implement final project01/10Demo result
Division of work Shih-Hao Lin HTIC Yi-Ming Huang AHB Master Keng-Chih Liu
Q: TIC and HTIC difference Functional test V.S. Structural test Test Stimuli
TIC and HTIC difference(1/2) AMBA Specification (Rev 2.0)