Presentation is loading. Please wait.

Presentation is loading. Please wait.

ECE 456 Computer Architecture

Similar presentations


Presentation on theme: "ECE 456 Computer Architecture"— Presentation transcript:

1 ECE 456 Computer Architecture
Fall'09 ECE 456 Computer Architecture Lecture #5 – Semiconductor (Internal) Memory Instructor: Honggang Wang Fall 2013

2 Administrative Issues (10/23/13, Wednesday)
Fall'09 Administrative Issues (10/23/13, Wednesday) Project proposal (File name: Group#_proposal.doc/docx) due Wednesday, Oct. 28 Proposal guidelines are available from the class website This class L#5 (Semiconductor Memory) Dr. Wang

3 Review of Lecture #4 In the last lecture, we covered the …...
Fall'09 Review of Lecture #4 In the last lecture, we covered the …... Characteristics of memory systems location, capacity, transfer unit, access methods, performance, physical types, physical characteristics, and organization Memory hierarchy dilemma, goal: why ? (locality), how? Error correction in memory error types, definitions & concepts, single-bit & multiple-bit parity codes, Hamming SEC Dr. Wang

4 Schedule for Memory Lectures
Fall'09 Schedule for Memory Lectures Next C A H E CPU MAIN MEMORY I/O STORAGE DEVICES Registers Internal Memory External Memory Defer to CPU discussion plus Virtual Memory Dr. Wang

5 Memory of Interest Location Physical types Access methods
Fall'09 Memory of Interest Location internal memory Physical types semiconductor memory Access methods random access memory Dr. Wang

6 Topics The basic elements Semiconductor memory types
Fall'09 Topics The basic elements Semiconductor memory types Memory organizations Dr. Wang

7 The Basic Elements: Memory Cells
Fall'09 The Basic Elements: Memory Cells Memory cell properties two stable states for representing binary 1 and 0 can be written into at least once to set the state can be read to sense the state Dr. Wang

8 Memory Cell Operations
Fall'09 Memory Cell Operations Dr. Wang

9 Agenda The basic element Semiconductor memory types
Fall'09 Agenda The basic element The memory cell Semiconductor memory types Memory organizations Dr. Wang

10 Semiconductor Memory Types (Internal and Random Access)
Fall'09 Semiconductor Memory Types (Internal and Random Access) Read-write memory Read-only memory Read-mostly memory Random-access memory (RAM) Read-only Memory (ROM) Programmable ROM (PROM) Erasable PROM (EPROM) Electrically Erasable PROM (EEPROM) Flash memory Static RAM (SRAM) Dynamic RAM (DRAM) Synchronous DRAM (SDRAM) Rambus DRAM (RDRAM) Cache DRAM (CDRAM) Dr. Wang

11 Random Access Memory (RAM)
Fall'09 Semiconductor Internal Random Access Memory Types – RAM (1) Random Access Memory (RAM) Can be both read and written Is volatile Can be used only as temporary storage Two forms: dynamic data tend to decay even with power continuously applied static data are held as long as power is supplied Dr. Wang

12 Agenda (RAM) Dynamic RAM (DRAM) Static RAM (SRAM) DRAM vs. SRAM
Fall'09 Semiconductor Internal Random Access Memory Types – RAM (2) Agenda (RAM) Dynamic RAM (DRAM) Static RAM (SRAM) DRAM vs. SRAM Enhancements to the DRAM SDRAM CDRAM Dr. Wang

13 Dynamic RAM (DRAM) Data stored as charge on capacitors
Fall'09 Semiconductor Internal Random Access Memory Types – RAM (3) Dynamic RAM (DRAM) Data stored as charge on capacitors presence: 1 absence: 0 threshold Need charge refreshing to maintain data storage A DRAM cell: read write Dr. Wang

14 Static RAM (SRAM) Data stored as a combination of transistors’ on-off
Fall'09 Semiconductor Internal Random Access Memory Types – RAM (4) Static RAM (SRAM) Data stored as a combination of transistors’ on-off T1, T4 off, T2, T3 on: 1 T1, T4 on, T2, T3 off: 0 Data are held as long as power is supplied, no refresh is needed A SRAM cell: Dr. Wang

15 DRAM vs. SRAM Volatile, Read-Write
Fall'09 Semiconductor Internal Random Access Memory Types – RAM (5) DRAM vs. SRAM Volatile, Read-Write DRAM cell Refresh needed Smaller and simpler More dense Less expensive For main memory SRAM cell No refresh Faster For cache memory Since both of them are RAM, as we discussed, they are both volatile, that is, power must be continuously supplied to the memory to retain the bit values. Also, both of them can perform read and write operations. For the dynamic cells, they need periodic charge refreshing to maintain the data storage. And each time when the data is read out, it must be written back or to say, the Data must be restored. For the static RAM, no refreshing is needed. As long as the power is supplied, the data will be held. From the structures of both memory cells, we can easily see that a dynamic RAM cell is simpler to build and smaller than a SRAM cell. Thus more DRAM cells can be put into a unit area, that is, DRAM is more dense and less expensive than a corresponding SRAM. On the other hand, a DRAM requires the supporting refresh circuitry. For larger memory, the fixed cost of the refresh circuitry is more than compensated for by the smaller variable cost of DRAM cells. Thus, the DRAM tends to be favored for large memory requirements. For example, the main memory uses DRAM. For SRAM, it’s generally faster than the DRAM, and more expensive, the SRAM is used for cache memories, both on-chip and off-chip. (in DRAM designs, the emphasis is on cost per bit and capacity, while SRAM designs are concerned with speed and capacity. Because of this concern, SRAM address lines are not multiplexed like DRAM: cutting the address lines in half, one half of address is sent first, called row access strobe, it is followed by the other half of the address, sent during the column access strobe. The DRAM is organized as a rectangular matrix addressed by row and columns. Actually, all the bits in the same row can be refreshed simultaneously. For example, for DRAM and SRAM designed in comparable technologies, the capacity of DRAMS is roughly 4 to 8 times that of SRAMs. The cycle time of SRAMs is 8 to 16 times faster than DRAMs. But they are also 8 to 16 times as expensive Dr. Wang

16 Agenda of RAM Dynamic RAM (DRAM) Static RAM (SRAM) DRAM vs. SRAM
Fall'09 Semiconductor Internal Random Access Memory Types – RAM (6) Agenda of RAM Dynamic RAM (DRAM) Static RAM (SRAM) DRAM vs. SRAM Example enhancements to the DRAM SDRAM CDRAM This is an agenda about the RAM discussion. First, we……. Lastly, we will look at the three enhancements to the DRAM architecture to complete our discussion about the RAM. Dr. Wang

17 Why Enhancements to DRAM?
Fall'09 Semiconductor Internal Random Access Memory Types – RAM (7) Why Enhancements to DRAM? Critical bottleneck: interface between the DRAM main memory and processor Cache solution is expensive and not enough Remember in our first lecture, we once talked about the performance balancing is a very critical issue in the computer system design. At that time we used this figure to show the lag between the processor speed growth and the DRAM speed growth. And the figure tells us that the processor speed and the DRAM capacity have grown rapidly, but the speed of the main memory has lagged badly. This speed will decide the speed with which the data can be transferred between and memory and the processor. When the memory fails to keep pace with the processor’s insistent demands, the processor should stall in a wait state, and valuable processing time is lost. Thus the interface between the main memory and CPU is the most critical pathway in the entire computer system since it is responsible for carrying a constant flow of instructions and data between memory chips and processor. With the high-performance processor, Such interface becomes the most critical bottleneck. To attack the performance problem of the DRAM main memory, designers has used a means by inserting one or more levels of high-speed SRAM cache between the DRAM main memory and the CPU. But as we just discussed, SRAM is much costlier than DRAM, and expanding cache size beyond a certain point yields diminishing returns. So, in recent years,a number of enhancements to the basic DRAM architecture have been explored. The two schemes that currently dominate the market are SDRAM and RDRAM.CDRAM is not on the market Now, but it is receiving considerable attention. Dr. Wang

18 Synchronous DRAM (SDRAM)
Fall'09 Semiconductor Internal Random Access Memory Types – RAM (8) Synchronous DRAM (SDRAM) Traditional DRAM Asynchronous CPU may wait for data/instructions from memory SDRAM access is synchronized to an external clock CPU knows when data can be ready (once-per-cycle) CPU can do something else while memory is processing request DDR-SDRAM: twice-per-cycle The traditional DRAM is asynchronous, thus when the memory speed fails to keep pace with the insistent demand of the CPU, the CPU will pause and wait. The valuable processing time is wasted. The system performance is slowed a lot. Unlike the conventional DRAM, the SDRAM exchanges data with the processor synchronized to an external clock signal thus, CPU will know when the data can be ready from memory, generally, The SDRAM can send data to the processor once per clock cycle,, either on the rising edge of the clock or the failing edge of the clock. Hence CPU does not have to wait, it can do something else while the memory is processing the read/write request. Also, now there is an enhanced version of SDRAM, known as double data rate SDRAM, this new version overcomes the SDRAM’s once-per-cycle limitation. It can send data to the processor twice per clock cycle, that is, data is transferred on both rising(leading) and failing(tailing) edge of the clock. (running at the full speed of the processor-memory bus without imposing the wait states). 8MB Synchronous DRAM DIMM f/LJ 4/5/8SERIES/MOP240EOL 02/01/00 Dr. Wang

19 Cache DRAM (CDRAM) Developed by Mitsubishi
Fall'09 Semiconductor Internal Random Access Memory Types – RAM (10) Cache DRAM (CDRAM) Developed by Mitsubishi Integrates a SRAM cache onto a DRAM chip A true cache A buffer to support serial access Dr. Wang

20 Fall'09 CDRAM Tokyo, January 15, Hitachi Ltd., today announced the high-performance 144-Mbit cache DRAM "HDL5KM series" with world-leading 8ns random access time and 4GB/s data bandwidth. Sample shipments will begin on June 1, 2004. Dr. Wang

21 Semiconductor Memory Types (Internal and Random Access)
Fall'09 Semiconductor Memory Types (Internal and Random Access) Read-write memory Read-only memory Read-mostly memory Random-access memory (RAM) Read-only Memory (ROM) Erasable PROM (EPROM) Static RAM (SRAM) Programmable ROM (PROM) Electrically Erasable PROM (EEPROM) Dynamic RAM (DRAM) Flash memory Synchronous DRAM (SDRAM) Rambus DRAM (RDRAM) Cache DRAM (CDRAM) Dr. Wang

22 Read-Only Memory (ROM)
Fall'09 Semiconductor Internal Random Access Memory Types – ROM (1) Read-Only Memory (ROM) Written only once during manufacturing Can be read, but cannot be written later Is nonvolatile, nonerasable Applications: microprogramming, system programs, library subroutines Advantage data/programs are permanently in main memory Problems costly for small runs, but attractive for high-volume runs no room for error Dr. Wang

23 Programmable ROM (PROM)
Fall'09 Semiconductor Internal Random Access Memory Types – ROM (2) Programmable ROM (PROM) Written only once after manufacturing Can be read, but cannot be written later Is nonvolatile, non-erasable Attractive for small production runs Advantages: flexible and convenient less expensive Dr. Wang

24 Erasable PROM (EPROM) Can be written many times
Fall'09 Semiconductor Internal Random Access Memory Types – Read-Mostly Memory (1) Erasable PROM (EPROM) Can be written many times Erased by ultraviolet radiation before each write operation at chip level Erasure (20 mins) can be performed repeatedly Is nonvolatile Pros & cons: Capable of multiple update More expensive than PROM Another variation on read-only memory is the read-mostly memory. Which is useful for applications in which read operations are far more frequent than write operations. But for which the nonvolatile storage is required. There are 3 common forms of RMM, EPROM< EEPROM<<Flash memory. The optically EPROM is read and written electrically. Only before a write operation, all the storage cells must be erased to the same initial state by exposure of packaged chips to ultraviolet radiation. Erasure is performed by shinning an intense UV light through a window that is designed into the mem chip. The erasure process can be performed repeatedly, each erasure can take about 20 minutes. Thus the EPROM can be altered multiple times. Like the ROM and PROM The EPROM is nonvolatile. No power is needed for retaining the data. As compared with PROM, the EPROM has the adv. Of the multiple update capability, but for comparable Amounts of storage, the EPROM is more expensive than PROM. Dr. Wang

25 Electrically EPROM (EEPROM)
Fall'09 Semiconductor Internal Random Access Memory Types – Read-Mostly Memory (2) Electrically EPROM (EEPROM) Erased and updated at the byte level Takes much longer to write than read Is nonvolatile More expensive and less dense than EPROM A more attractive form of RMM is EEPROM. It can be written into at any time without erasing all the Previous contents; only the byte or bytes addressed are updated. Also, the write operation takes considerably longer than the read operation. Still the EEPROM is nonvolatile. But Eeprom is more expensive and less dense (supporting fewer bits per chip) than the EPROM. Dr. Wang

26 Fall'09 Semiconductor Internal Random Access Memory Types – Read-Mostly Memory (3) Flash Memory Intermediate between EPROM and EEPROM in both cost and functionality Electrical and fast erasure (a few seconds/memory) Can be erased at block level Another form of RMM is flash memory. Flash memory gets its name because a section of memory cells can be erased in a single action or flash. It’s much faster than EPROM(20 mins, but should be less than EEPROM, on the order of several hundred microseconds per byte). As in EEPROM, flash memory uses an electrical erasing technology. However, the flash memory does not provide byte-level erasure. The flash memory can erase blocks of memory. This is better than EPROM which erase at the chip level. Dr. Wang

27 Agenda The basic element Semiconductor memory types
Fall'09 Agenda The basic element The memory cell Semiconductor memory types RAM, DRAM, SRAM; SDRAM, RDRAM, CDRAM ROM, PROM EPROM, EEPROM, flash memory Memory organizations Dr. Wang

28 Two Extremes In Organization (1)
Fall'09 Two Extremes In Organization (1) Physical arrangement of cells in the array is the same as the logical arrangement of words in memory (one-word-per-chip) A 256 KByte chip can be organized as 256K 8-bit words One-bit-per-chip organization Each chip provides 1 bit input/output at a time A 256 KByte one-bit-per-chip system has 8 lots of 256Kbit chip with bit 1 of each word in chip/lot 1, and so on Dr. Wang

29 256-KByte Memory One-word-per-chip Organization
Fall'09 Two Extremes In Memory Organization (2) 256-KByte Memory One-word-per-chip Organization 256K rows of 8-bit words 18 address lines bit7 bit0 Word 0 1word = 8bits . A0 Address Decoder A1 . A17 Word 256K-1 Dr. Wang

30 256-KByte Memory One-bit-per-chip Organization
Fall'09 Two Extremes In Memory Organization (3) 256-KByte Memory One-bit-per-chip Organization 512 x 512 per chip 18 address lines 9 for row 9 for column Dr. Wang

31 16-Mbit Memory Organization (1) DRAM
Fall'09 Examples of Memory Organizations (I) 16-Mbit Memory Organization (1) DRAM Dr. Wang

32 16-Mbit Memory Organization (2) DRAM
Fall'09 Examples of Memory Organizations (I) 16-Mbit Memory Organization (2) DRAM Organized as a 2048 x 2048 x 4bit array The physical arrangements is one-word-per-chip Reduced number of address pins Multiplexed row address and column address 11 pins, rather than 22 pins Adding 1 more pin doubles number of rows and columns and so x4 capacity Refresh circuit included on chip Refreshed by reading out data and writing back Cells in the same row are refreshed simultaneously So, here is a summary about the 16 Mbit Memory organization. Dr. Wang

33 16-Mbit DRAM (3) Chip Packaging
Fall'09 Examples of Memory Organizations (I) 16-Mbit DRAM (3) Chip Packaging A0-A10: multiplexed address D1-D4: data WE: write enable OE: output enable RAS/CAS: row/column address select Vcc: voltage source Vss: ground NC: no connect, for even # Dr. Wang

34 8-Mbit Memory Organization (1)
Fall'09 Examples of Memory Organizations (II) 8-Mbit Memory Organization (1) Dr. Wang

35 8-Mbit Memory Organization (2)
Fall'09 Examples of Memory Organizations (II) 8-Mbit Memory Organization (2) Organized as a 512 x 512 x 32 bit array The physical arrangements is one-bit-per-chip 4 columns of chips, each containing 256K words (512 x 512 x 8 bits) Group select logic select one of 4 columns 20 address pins 18 pins for selecting 1 of 512 x 512 bits 2 pins for selecting 1 0f 4 columns No refresh circuit is needed Ok, here is a summary about the above 8 Mbit memory organization: Dr. Wang

36 8-Mbit EPROM (3) Chip Packaging
Fall'09 Examples of Memory Organizations (II) 8-Mbit EPROM (3) Chip Packaging A0-A19: address D0-D7: data CE: chip enable Vcc: power supply Vss: ground Vpp: program voltage, supplied during programming/writing Dr. Wang

37 Fall'09 Hands-on Problems There are two extreme designs in memory organization: “one-word-per-chip” and “one-bit-per-chip”.   Design a 4-Kbyte memory using each of the two design strategies. Dr. Wang

38 Summary of Lecture #5 The basic element Semiconductor memory types
Fall'09 Summary of Lecture #5 The basic element The memory cell Semiconductor memory types RAM, DRAM, SRAM; SDRAM, RDRAM, CDRAM ROM, PROM EPROM, EEPROM, flash memory Memory organizations One-word-per-chip One-bit-per-chip Examples: 16 Mbit, 8 Mbit, 256 KByte Dr. Wang

39 Next topic: Cache Memory
Fall'09 Next topic: Cache Memory C A H E CPU MAIN MEMORY I/O STORAGE DEVICES Registers Internal Memory External Memory Defer to CPU discussion plus Virtual Memory Dr. Wang

40 Things To Do Project proposal Check out the class website about
Fall'09 Things To Do Project proposal due Oct. 28, Wednesday Check out the class website about lecture notes reading assignments the project Dr. Wang

41 Fall'09 Solution Dr. Wang

42 SAMSUNG 512MB 800MHZ 184PIN RAMBUS MEMORY
Fall'09 SAMSUNG 512MB 800MHZ 184PIN RAMBUS MEMORY                                                                                                          Dr. Wang

43 KINGSTON 256MB 800MHZ 184PIN RAMBUS MEMORY
Fall'09 KINGSTON 256MB 800MHZ 184PIN RAMBUS MEMORY Dr. Wang


Download ppt "ECE 456 Computer Architecture"

Similar presentations


Ads by Google