1. The Instruction Set Architecture Level Dept. of Computer Science Virginia Commonwealth University

2. CMSC 312 Computer Organization Hongsik Choi 2 ISA level Interface between the software and hardware Common intermediate formBuild H/W, execute ISA program directly Build compiler

3. CMSC 312 Computer Organization Hongsik Choi 3 5.1. properties Defined by how the machine appears to a machine language programmer Memory model, registers, data types and instructions, etc

4. CMSC 312 Computer Organization Hongsik Choi 4 5.1.2 Memory Models Memory: collection of addressable cells Byte: ASCII Unicode

5. CMSC 312 Computer Organization Hongsik Choi 5 5.1.2 Memory Models Aligned? Single Linear address space? Memory semantics DataProgram Read/write Serialized/Sync instruction

6. CMSC 312 Computer Organization Hongsik Choi 6 5.1.3 Registers Registers – visible to micro architecture level Some are visible to ISA Level (\TOS, MAR) special purpose (SP, PC) control registers for kernel mode PSW (Program Status Word) condition codes (bits in PSW) N,Z,V,C,A,P general purpose (local variables, etc)

7. CMSC 312 Computer Organization Hongsik Choi 7 5.1.3 Instructions Load, store Move Arithmetic Logic

8. CMSC 312 Computer Organization Hongsik Choi 8 5.1.5 Pentium 4 ISA level Level 0 : kernel mode Level1: Level2: Level 4: User mode 2 32 02 13 -1

9. CMSC 312 Computer Organization Hongsik Choi 9 5.1.5 Pentium 4 ISA level Main arithmetic register Good for holding pointers Play a role in looping For * and / Pointer(M) to the source Pointer(M) to the destination Base of current stack frame Stack pointer Segment registers Instruction Pointer (PC) PSW

10. CMSC 312 Computer Organization Hongsik Choi 10 5.1.6 UltraSPARC III ISA Level RISC machine 2 64 32 64bit GPR and 32 bit floating point registers FP: Frame pointer SP: stack pointer CWP: current window pointer Multiple GPRs set Only STORE, LOAD can access memory

11. CMSC 312 Computer Organization Hongsik Choi 11 5.1.6 UltraSPARC III ISA Level 1. Emulate stack w/ Procedure call 2. Fast parameter passing 8 Global registers

12. CMSC 312 Computer Organization Hongsik Choi 12 5.1.7 8051 ISA Level (embedded system) One chip with CPU, memory and I/O controller 64K for data 64k for programs ROM RAM For rapid interrupt processing 8 bit R0 to R7 128 255 Special registers Such as accumulator (240)

13. CMSC 312 Computer Organization Hongsik Choi 13 5.2 Data Types at the ISA level,meaning data types supported by hardware Numerical data types, (2 32-1, or 2 31-1, Non numerical data types, Data types on the Pentium 4, SPARC and 8051 n = f x 10 e, fraction( or mantissa), exponent 3.14 = 0.314 × 101 = 3.14 × 100 0.000001 = 0.1 × 10−5 = 1.0 × 10−6 1941 = 0.1941 × 104 = 1.941 × 103

14. CMSC 312 Computer Organization Hongsik Choi 14 5.2.1. Numerical data types Integer( unsigned 2 32-1, or signed 2 31-1) n = f x 10e, fraction( or mantissa), exponent 3.14 = 0.314 × 101 = 3.14 × 100 0.000001 = 0.1 × 10−5 = 1.0 × 10−6 1941 = 0.1941 × 104 = 1.941 × 103 F = 3 digit in the range of 0.1 <= f < 1, e = zero and signed 2 digit -0.999x10 99, -0.100x10- 99, 0, 0.100x10- 99, 0.9 99 x 10 99 Real N = continuum Floating P N = 2* 179100 + 1 Rounding (nearest number) 0.9998x10 99 vs 0.999x10 99

15. CMSC 312 Computer Organization Hongsik Choi 15 5.2.2. Nonumerical data types ASCII(7) vs UNICODE(16) Boolean Machine address

16. CMSC 312 Computer Organization Hongsik Choi 16 5.2.3. Pentium, Sparc, and 8051

17. CMSC 312 Computer Organization Hongsik Choi 17 5.3. Instruction Format

18. CMSC 312 Computer Organization Hongsik Choi 18 5.3.1 Design criteria for instructionFormats Size of instruction? n-16 bit instruction vs n -32 bit instruction Memory size, fetch speed vs harder to decode, more time to decode and execute Accommodate all the operation desired. 2 n operation with n-1 bit? Size of address field? Memory (2 32 bytes) If 8bit byte as a basic unit of word vs 32 bit word vs 1 bit (Burroughs B1700) Resolution shorter address means shorter instruction vs. Waste space, Extra comparison

19. CMSC 312 Computer Organization Hongsik Choi 19 5.3.2 Expanding Opcodes (n+k) bit instrcution If 2 n memory cell, we have only 2 k opcodes With 16 registers What if we have15 three address instn, 14 two address instn, 31 one address instn and 16 no address instn? Size of instruction n-16 bit instruction vs n -32 bit instruction Memory size, fetch speed vs harder to decode, more time to decode and execute

20. CMSC 312 Computer Organization Hongsik Choi 20 5.3.2 Expanding Opcodes We have variable size opcode to make the unit size instructions. Variable size instruction is hard to decode, even hard to align on byte boundaries

21. CMSC 312 Computer Organization Hongsik Choi 21 5.3.3. case studies 1,2,3 byte