1. Chapter 10: 68HC11 Serial Peripheral Interface
The 68HC11 Microcontroller
Han-Way Huang
Minnesota State University, Mankato

2. Why SPI?
- The number of I/O port pins are limited on an 8-bit microcontroller.
- It is desirable to implement more I/O functions on the same number of port pins.
- Many I/O devices do not require high speed.
- SPI allows more I/O functions to be supported on the 68HC11.
A Summary of the 68HC11 SPI System
- Two types of devices are involved in data transfer in the SPI format: master and
slaves
- Multiple SPI compliant devices can be interconnected
- The master device initiates data transfer and also generates the clock signal
required for data transfer synchronization
- The 68HC11 SPI is often used for I/O port expansion, and interfacing with
peripheral devices such as LED/LCD display drivers, phase-locked loop chips,
A/D and D/A converters, serial EEPROMs, serial SRAMs, etc.

3. SPI Pins
- SS/PD5: slave select
- SCK/PD4: serial clock
- MOSI/PD3: master out slave in
- MISO/PD2: slave out master in

4. SPI-Related Registers
1. The Serial Peripheral Control Register (SPCR)
SPIE: SPI interrupt enable
SPE: SPI enable
DWOM: port D wired-or mode select
MSTR: SPI master or slave select
CPOL: clock polarity. 1: SCK idle high, 0: SCK idle low
CPHA: SCK clock phase. Control the clock-data relationships
between the master and slave. CPHA and CPOL must be
used together. See Figure 9.1.
SPR1 & SPR0: SPI clock rate select

6. Serial Peripheral Status Register (SPSR)
Port D Data Direction Register (DDRD)

7. SPI Circuit Connection
1. Single master single slave

8. 2. SPI Single master and multiple slaves circuit connection I
- The SPI master can selectively exchange data with any slave.
- By disconnecting the MISO pin, the master can output data to one or multiple slaves at
the same time.

9. 3. SPI Single master and multiple slaves circuit connection II
- All slaves are connected into a large shift register chain.
- The master cannot selectively exchange data with a single slave.

10. SPI Data Transfer 1. The procedure
- An SPI transfer is initiated by writing data to the shift register in the master SPI device.
- Data is circuited 8 bit positions; thus data is exchange between the master and the slave.
- The master SPI device sends out 8 pulses from the SCK pin to synchronize data transfer.
- After 8 bits have been transferred, the SPIF flag of the SPSR register will be set to 1.
2. Error conditions
- write collision: a write is performed during an SPI data transfer. The write will be
unsuccessful and the WCOL bit of the SPSR register will be set to 1.
- mode fault: the SS input of a master is asserted low. The SPI master that has a mode
fault will:
(1) generate an SPI interrupt if SPIE = 1
(2) clear SPE flag to disable the SPI
(3) clear the MSTR bit forcing itself into the slave mode
(4) force the DDRD bits to zeros for the four SPI pins.

11. 3. The program to transfer data from the master to a slave
regbas equ $1000 ; base address of the I/O register block
SPDR equ $2A ; offset of SPDR from regbas
SPCR equ $28 ; offset of SPCR from regbas
SPSR equ $29 ; offset of SPSR from regbas
DDRD equ $09 ; offset of DDRD from regbas
SPI_DIR equ $38 ; value to set SS, SCK and MOSI pins for output and MISO for input
SPI_INI equ $54 ; value to initialize the SPI which will enable SPI, disable SPI
* ; interrupt, configure port D pins as normal CMOS pins, select
* ; master mode, choose the falling edge of SCK to shift data, and
* ; sets data rate to 1 Mbits/sec at 2 MHz E clock
ORG $00
data RMB $10 ; a data buffer .
ldx #regbas
ldaa #SPI_DIR
staa DDRD,X ; set port D directions
ldaa #SPI_INI
staa SPCR,X ; initialize the SPI operation parameters
ldaa data
staa SPDR,X ; start SPI transfer
wait ldab SPSR,X ; wait for data to be sent out
bpl wait ; “

12. 3. The program to read data from a slave
ldx #regbas
ldaa #SPI_DIR
staa DDRD,X
ldaa #SPI_INI
staa SPCR,X
staa SPDR,X ; start an SPI transfer
here ldab SPSR,X ; wait until 8 bits have been shifted in
bpl here ; “
ldaa SPDR,X ; place the byte in A .

13. Simulating the SPI
If data is shifted on the falling edge of the clock signal:
Step 1: Set the clock to high.
Step 2: Apply the data bit on the port pin that is connected to the serial data input pin of the
peripheral device.
Step 3. Pull the clock to low.
Step 4. Repeat steps 1 to 3 for as many times as needed.
If the rising edge is used to shift data, then
- set clock to low in step 1
- set clock to high in step 3

14. Shift register HC589

15. HC589 Operation
1. The parallel data inputs (A,…,H) will be loaded into the data latch on the rising edge of
the latch clock.
2. When the serial shift/parallel load signal is low, the data in the data latch will be loaded
into the shift register. Otherwise, the shift register is enabled to shift.
3. When the shift register is enabled to shift, the serial data input SA will be shifted into
the shift register and the data on stage H will be shifted out from pin QH.
4. The output enable signal (pin 10) must be low in order for data at stage H be driven out
from pin QH.
Application of HC589
- to expand the number of parallel input ports of 8-bit microcontrollers.
- convert parallel data into serial format

16. Interfacing the HC589 to the SPI
Method 1.

17. Method I (continued)
procedure for data transfer:
Step 1. Program the DDRD register to configure SCK, TxD, and SS pins for output and
the MISO pin for input.
Step 2. Program the SPCR register to enable the SPI function and set up other parameters.
Step 3. Set the LC pin to low and then pull it to high; this will load the external data into
the data latch in parallel.
Step 4. Set the SS pin to low to select the parallel load mode, which will load the contents
of the data latch into the shift register.
Step 5. Set the SS pin to high to select the serial shift mode.
Step 6. Write a byte into the SPDR register to trigger eight SCK clock pulses to shift in
8 bits.
Step 7. Repeat step 6 as many times as needed, and save the data in a buffer.

18. Example 10.1 Write a program to input 8 bytes from 8 external HC589s connected as shown
in Figure 10.6 and store the data at locations $00-$07.
Solution:
Configure the SS, SCK, MOSI, and TxD pins for output and MISO and RxD pins for input --
write the value % ($3A) into DDRD.
Write the value % ($50) into the SPCR register to:
1. disable SPI interrupt
2. enable the SPI
3. set port D pins for normal CMOS output pins (not open drain)
4. use the rising edge of the SCK signal to shift data
5. select a 1-Mbits/sec data rate
regbas equ $1000
PORTD equ $08
DDRD equ $09
SPCR equ $28
SPSR equ $29
SPDR equ $2A
SPCR_INI equ $50
SPI_DIR equ $3A

19. org $C000
ldx #regbas
ldaa #SPI_DIR
staa DDRD,X ; configure SPI pin directions
ldaa #SPCR_INI
staa SPCR,X ; initialize SPI operation parameters
* The following two instructions load data into HC589s in parallel
bclr PORTD,X $02 ; pull TxD (LC) to low
bset PORTD,X $02 ; pull TxD (LC) to high
bclr PORTD,X $20 ; pull SS pin to low to select parallel load mode and load
; the contents of the data latch into the shift register
bset PORTD,X $20 ; pull SS pin to high to select serial shift mode
ldab #8 ; loop count for transferring 8 bytes
ldy #$0000 ; set Y to point to the buffer
loop staa SPDR,X ; trigger SPI data transfer
brclr SPSR,X $80 * ; wait until 8 bits have been shifted
ldaa SPDR,X ; get one byte
staa 0,Y ; save the data
decb ; decrement loop count
bne loop
end

20. In C language,
#include <hc11.h>
main ( ) {
char buffer[8], i;
DDRD = 0x3A; /* configure port D pins directions */
SPCR = 0x50; /* configure SPI parameters */
PORDT &= 0xFD; /* create a rising edge on the TxD pin */
PORTD |= 0x02; /* to load data into data latch */
PORTD &= 0xDF; /* transfer data from data latch to shift register */
PORTD |= 0x20; /* select serial shift mode */
for (i = 0; i < 8; i++) {
SPDR = 0x00; /* shift data in from the MISO pin */
while (!(SPSR & 0x80)); /* wait for data to shift in */
buffer [i] = SPDR; }
return 0;

21. Interfacing the HC589 to the SPI -- Method II

22. Procedure for data transfer (method II)
Step 1. Program the DDRD register to set the directions of the MISO, SCK, SS, and TxD pins.
Step 2. Program the SPCR register to configure the SPI operation parameters.
Step 3. Set the TxD pin to low and then pull it to high to load external data into the data latch
in parallel.
Step 4. Set the SS pin to low to select the parallel load mode, which will load the contents of
the data latch into the shift register.
Step 5. Pull the SS pin to high to select the serial shift mode.
Step 6. Set the port B that controls the specified HC589 to low to enable the shift register to
output serial data. The remaining port B pins are set to high.
Step 7. Write a byte into the SPDR register to trigger eight pulses from the SCK pin to shift
in the serial data. The external data is now in the SPDR register and ready for use.
Step 8. Repeat steps 6 and 7 as many times as needed.

23. Shift Register HC595

24. HC595 Operation
- The shift register accepts serial data and provides a serial output.
- The serial data input (A) is shifted into the shift register on the rising edge of the shift clock.
- The data in the shift register will be loaded into the output latch on the rising edge of the
latch clock.
- A low on the output enable pin allows data from the latch to be presented at the output
pins QA-QH.
- The serial output SQH does not have tri-state capability.
- Multiple HC595s can be cascaded to expand the number of parallel output ports for
the 68HC11.

25. Interfacing HC595 to the SPI -- Method I

26. Method I (continued)
Data transfer procedure
Step 1. Program the DDRD register to configure SPI pin directions.
Step 2. Program the SPCR register to set up appropriate SPI operating parameters.
Step 3. Write a byte into the SPDR register to trigger eight pulses from the SCK pin.
Step 4. Repeat step 3 as many times as needed.
Step 5. Set the SS pin to low and then pull it to high to transfer the byte in the shift
register into the output latch. After this step, the output latch contains valid
data.
Example 9.2 Write a program to output three bytes to the first three HC595s in Figure 9.8.
Solution:
regbas equ $1000
PORTD equ $08
DDRD equ $09
SPCR equ $28
SPDR equ $2A
SPSR equ $29

27. SPI_DIR equ $3A ; value to configure SPI pin directions
SPCR_IN equ $50 ; value to enables SPI, disables SPI interrupt, chooses rising
* ; edge of SCK to shift data, selects normal port D pins,
* ; and sets data rate to 1 Mbits/sec.
K equ 3
org $00
buffer fcb $11,$22,$33
org $C000
ldx #regbas
ldaa #SPI_DIR
staa DDRD,X ; configure pins SS, MOSI, SCK, and TxD for output
ldaa #SPCR_IN
staa SPCR,X ; configure SPI operation parameters
ldab #K ; set up loop count
ldy #buffer ; set Y as a pointer to the buffer
ch_loop ldaa 0,Y ; send out one byte via SPI function
staa SPDR,X ; “
brclr SPSR,X $80 * ; wait until the byte is shifted out
iny ; move the buffer pointer
decb ; decrement the loop count
bne ch_loop
bclr PORTD,X $20 ; create a rising edge on SS pin to load data into output
bset PORTD,X $20 ; latch
end

28. Interfacing the HC595 to the SPI -- Method II

29. Method II:
Data transfer procedure
Step 1. Program the DDRD register to set up SPI pin directions.
Step 2. Program the SPCR register to enable the SPI subsystem, select the data rate, select
the rising edge of SCK signal for data shifting, select master mode, and disable
interrupt.
Step 3. Write a byte into SPDR to trigger SPI data transfer.
Step 4. Set the PBi pin to low and then pull it to high to load the byte from the shift register
of the HC595 i into its output latch.

30. The Seven-Segment Display Driver Chip MC14489

31. MC14489 Pins
Data In: A serial data input pin.
Clock: The rising edge of this signal is used to shift data into the shift register. The
highest shift clock frequency is 4 MHz.
Enable: External data can be entered when this signal is low. The data are loaded from the
shift register into the latches on the rising edge of this signal.
a thru h: Seven-segment outputs for driving seven segments and decimal point LEDs.
Bank 1..5: Digit select pins. The MC14489 can drive up to five seven-segment displays, but
only one seven-segment display is lighted at any time. The display to be lighted is
selected by these pins.
Rx: External current-setting resistor. The relationship between the segment current and
Rx is shown in Figure

33. The MC14489 Operation
- The configuration register controls the MC14489 operation.
- Two operation modes: hex mode and special decode. The decode function is
shown in Table 10.1.
- Displays can be made dimmer or brighter by clearing or setting the first bit of
the display data sent to the MC14489.

35. Interfacing the MC14489 to the 68HC11 SPI

36. - One byte of configuration information and 3 bytes of display data must be
sent to the MC14489 in Figure
- The 4 most significant bits control the brightness and display of h segments as
shown in Figure

37. Example 10. 3 Write a program to display 997
Example 10.3 Write a program to display from bank 5 to bank 1 in Figure Use
the normal brightness to display these five digits.
Solution:
The control byte to be written into the configuration register is as follows:
bit 7: no decode, set to 0
bit 6: no decode, set to 0
bit 5: bank 5 hex decode, set to 0
bit 4: bank 4 hex decode, set to 0
bit 3: bank 3 hex decode, set to 0
bit 2: bank 2 hex decode, set to 0
bit 1: bank 1 hex decode, set to 0
The display data format is

38. The Configuration of SPCR register:
bit 7 (SPIE): set to 0 to disable interrupt
bit 6 (SPE): set to 1 to enable SPI function
bit 5 (DWOM): set to 0 to choose normal port D pins
bit 4 (MSTR): set to 1 to select master mode
bit 3 & 2 (CPOL & CPHA): set to 00 to use rising edge to shift data out
bit 1 & 0 (SPR1 & SPR0): set to 00 to choose 1 MHz shift rate
regbas equ $1000
PORTD equ $08
DDRD equ $09
SPCR equ $28
SPDR equ $2A
SPSR equ $29
SP_DIR equ $3A ; value to configure SPI pins directions
SPCR_IN equ $50 ; value to set up the specified SPI operation parameters

39. ORG $00
disp_dat FCB $B9,$97,$04
ORG $C000
LDX #regbas
LDAA #SP_DIR
STAA DDRD,X ; configure SPI pin directions
LDAA #SPCR_IN
STAA SPCR,X ; initialize the SPI parameters
BCLR PORTD,X $20 ; enable data shifting to MC14489
LDAA #$01
STAA SPDR,X ; send out configuration data to MC14489
BRCLR SPSR,X $80 * ; wait until configuration data has been shifted out
BSET PORTD,X $20 ; latch data into configuration register
BCLR PORTD,X $20 ; enable SPI data transfer to MC14489
LDY #disp_dat
LDAB #3
loop LDAA 0,Y
STAA SPDR,X
BRCLR SPSR,X $80 *
INY
DECB
BNE loop
BSET PORTD,X $20 ; load data into display data register
END

40. A C Program for Sending Data to MC14489
#include <hc11.h>
main ( ) {
int i;
unsigned char disp_dat[3] = {0xB9, 0x97, 0x04};
DDRD = 0x3A;
SPCR = 0x50;
PORTD &= 0xDF; /* enable SPI data transfer to MC14489 */
SPDR = 0x01; /* send out configuration data */
while (!(SPSR & 0x80)); /* wait until data have been shifted out */
PORTD |= 0x20 /* load data into configuration register */
PORTD &= 0xDF; /* enable SPI transfer to MC14489 */
for (i = 0; i < 3; i++) {
SPDR = disp_dat [i];
while (!(SPSR & 0x80)); }
PORTD |= 0x20;
} /* load data into display data register */

41. Cascading MC14489s
- Connect the Data Out pin of one MC14489 to the Data In pin of the next MC14489.
- To configure n MC14489s, we need to send out 3 × (n -1) + 1 bytes of data
to the MC14489s. Only n bytes are used to configure the MC14489s.
- A circuit of cascading three MC14489s is illustrated in Figure

42. Three bytes of configuration data must be sent to three MC14489s:
Example 10.8 Write a program to display the following information (temperature at
14:20 of Aug. 2nd, 1999) on the 15 seven-segment displays driven by three
MC14489s as shown in Figure 10.17:
30.5oC
Solution:
- Use the special decode of character F to represent the character for degree.
- Represent all other characters using normal decode method.
- The left-most five digits are displayed by the MC14489 #1.
- The middle five digits are displayed by the MC14489 #2.
- The right-most five digits are displayed by the MC14489 #3.

43. Configurations of three MC14489s
C7: set to 0 to select no decode
C6: set to 1 to select special decode (display degree character on bank 2)
C5..C3: set to 0 to select hex decode
C2: set to 1 to select special decode
C1: set to 0 to select hex decode
C0: set to 1 to select normal mode
MC14489 #2 & #3:
C7 & C6: set to 0 to select no decode
C5..C1: set to 0 to select hex decode
- The configuration data for the MC14489 #3 should be sent out first.
- The complete configuration data is 01xxxx01xxxx45, where x strands for don’t
care and should be set to 0.

44. Display Data for MC14489 #1
Display Data for MC14489 #2
Display Data for MC14489 #3

45. REGBAS EQU $1000
SPSR EQU $29
SPDR EQU $2A
SPCR EQU $28
PORTD EQU $08
DDRD EQU $09
ORG $C000
LDX #REGBAS
LDAA #$3A
STAA DDRD,X ; configure SPI pin directions
LDAA #$50
STAA SPCR,X ; configure SPI parameters
LDAB #7
BCLR PORTD,X $20 ; enable SPI transfer to MC14489s
LDY #conf_dat ; set Y to point to configuration data
loop1 LDAA 0,Y
STAA SPDR,X
BRCLR SPSR,X $80 * ; wait until a byte has been shifted out
INY
DECB
BNE loop1
BSET PORTD,X $20 ; load data into configuration registers

46. BCLR PORTD,X $20 ; enable SPI transfer to MC14489s
LDY #disp_dat
LDAB #9
loop2 LDAA 0,Y
STAA SPDR,X
BRCLR SPSR,X $80 *
INY
DECB
BNE loop2
BSET PORTD,X $20 ; load data into display data register
… ; do something else
conf_dat DB $01,$00,$00,$01,$00,$00,$45
disp_dat DB $88,$02,$99,$81,$20,$00,$C2,$55,$FC

47. In C language
#include <hc11.h>
main ( ) {
int i;
unsigned char conf_dat [ ] = {0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x45};
unsigned char disp_dat [ ] ={0x88, 0x02, 0x99, 0x81, 0x20, 0x00, 0xC2, 0x55, 0xFC};
DDRD = 0x3A;
SPCR = 0x50;
PORTD &= 0xDF; /* enable SPI transfer to MC14489s */
for (i = 0; i < 7; i++) {
SPDR = conf_dat[i];
while (!(SPSR & 0x80)); }
PORTD |= 0x20; /* load data into configuration registers */
for (i = 0; i < 9; i++) {
SPDR = disp_dat [i];
while (!(SPSR 7 0x80));
PORTD |= 0x20; /* load data into display data registers */
return 0;

48. Liquid Crystal Displays (LCDs)
- LCDs are often multiplexed to save connection pins.
- Motorola has LCD drivers that drives 1/4 multiplexing LCDs.
- In a 1/4 multiplexing LCD, each character is represented by a multiple of four segments.
- An LCD display that displays BCD digit consists of seven segments and an optional
decimal point.
- An LCD segment is turned on and off by controlling the backplane and frontplane voltages.
- Each BCD digit is controlled by two frontplane and four backplane signals.
- There is no standard for backplane and frontplane connections on multiplexed LCD displays.

49. The MC145000 and MC145001 LCD drivers

51. Operation of the MC145000
- Display data bits are shifted in on the falling edge of the data clock.
- Data in the shift register are loaded into the 48-bit latch at the beginning of each frame
period.
- The frame period is the time during which all the LCD segments are set to the desired on
or off states.
- The data in the shift register of the LCD driver is loaded into the latch that drives the
frontplane outputs when the frame-sync pulse is high.
- New data should not be shifted in in this period to avoid flicker.
- Backplane waveforms are invariant.
- The frontplane and backplane waveforms, FPn and BPn, are generated using the system
clock and voltages from the V/3 generator circuit.
- Examples on backplane and frontplane waveforms are given in Figure 10.26,
Operation of the MC145001
- This unit consists of the same circuitry as the master unit, with two exceptions: it has no
backplane driver circuitry, and its shift register and latch hold 44 bits.

55. Clock Signal Issue
- OSCin is the input to the system clock circuit.
- OSCout is the system clock output generated by the master unit.
- The OSCout signal from the master unit is connected to the OSCin input of all slave units
to synchronize updating of display data.
- The oscillator frequency can be obtained from an external oscillator or by connecting an
resistor between OSCin and OSCout.
- The relationship between oscillator frequency and resistor value is shown in Figure

57. LCD display pattern
- The LCD controller multiplexes four bits to drive the same frontplane output pin.
- The master unit also activates the corresponding backplane output to turn segments on
and off.
- The bit locations (in the latch) that control the master unit LCD segments located at each
frontplane-backplane intersection are shown in Table 10.3.
- The order for shifting the segment patterns into the LCD driver is a, b, c, d, e, f, g, and h.
- The hexadecimal representation of BCD digits LCD display patterns are shown in
Table 10.3.

59. LCD driver system configuration
- One master and one or multiple slave LCD drivers can be cascaded when more than six
digits are to be displayed (shown in Figure 10.30).
- Data are shifted serially first into the master unit and then into the following slave units
on the falling edge of the common data clock.
- At the beginning of each frame period, the master unit generates a frame-sync pulse to
synchronize to the master unit’s backplane drive circuit.
- The master unit generates the backplane signals for all the LCD digits in the system.

60. An LCD from LXD -- part #69

61. - The backplane signal BP1 is assigned to pins 60 and 59.
- Ai, Bi, Ci, Di, Ei, Fi, Gi, and DP stand for the segments and decimal point of the ith digit.
- A pin associated with some segment letter is a frontplane pin.
- Up to 8 digits can be displayed using this LCD.

62. Using an MC145000 and an eight-digit LCD from LXD to display 6 digits
- The 1 MW resistance sets the oscillator frequency to 24 KHz.
- The system frequency is obtained by dividing the previous frequency by 256 and is
94 Hz.

63. Example 10.5 Write a program to display 123456 on the LCD in Figure 10.33.
Solution:
- Configure pins SS, MOSI, SCK, and Tx for output and the other port D pins for input.
- Configure the SPI to operate with the following parameters:
1. SPI interrupt disabled
2. SPI function enabled
3. normal port D pins
4. master mode
5. shifting data using the falling edge of the SCK signal
6. 1 Mbits/sec data rate
Write the value $54 into the SPCR register
- Send 48 0s to the LCD driver to clear the LCD digits.

64. regbas EQU $1000 ; base address of I/O register block
DDRD EQU $09 ; offset of DDRD from regbas
SPCR EQU $28 ; offset of SPCR from regbas
SPSR EQU $29 ; offset of SPSR from regbas
SPDR EQU $2A ; offset of SPDR from regbas
DD_INI EQU $3A ; value to set the DDRD register
SPCR_INI EQU $54 ; value to be written into the SPCR register
ORG $00
digits FCB 1,2,3,4,5,6 ; digits to be displayed
lp_cnt RMB 1 ; loop count
ORG $C000
LDS #$3F ; set up stack pointer for EVB computer
LDX #regbas
LDAA #DD_INI
STAA DDRD,X ; configure port D pin directions
LDAA #SPCR_INI
STAA SPCR,X ; configure SPCR register
* The following 6 instructions send out 6 0’s to clear LCDs
LDAB #6
loop CLRA
STAA SPDR,X
BRCLR SPSR,X $80 * ; wait for 8 bits to be shifted out
DECB
BNE loop

65. LDY #digits ; point Y to the start of the digit table
LDAB #6
STAB lp_cnt ; initialize the loop count
loop1 LDAB 0,Y ; get the digit to be displayed
PSHY ; save Y in the stack
LDY #lcdndp ; place LCD pattern table address in Y
ABY ; index into the LCD pattern table
LDAA 0,Y ; get the LCD pattern from the table
STAA SPDR,X ; send out the digit pattern
BRCLR SPSR,X $80 * ; wait until the digit pattern has been shifted out
PULY ; restore the value of Y from the stack
INY ; move the digit pointer
DEC lp_cnt ; decrement the loop count
BNE loop1 .
* The following lines contain the LCD display patterns of hexadecimal digits
lcdndp FCB $EB,$60,$C7,$E5,$6C,$AD,$2F,$E0,$EF,$EC
FCB $EE,$0A,$6A,$6B,$04,$00
END

66. In C Language,
#include <hc11.h>
main ( ) {
int i;
char digits [ ] = {1, 2, 3, 4, 5, 6};
hex_pat [ ] = {0xEB, 0x60, 0xC7, 0xE5, 0x6C, 0xAd, 0x2F, 0xE0, 0xEF, 0xEC,
0xEE, 0x0A, 0x6A, 0x6B, 0x04, 0x00};
DDRD = 0x3A; /* configure SPI pin directions */
SPCR = 0x54; /* configure SPCR register */
for (i = 0; i < 6; i++) { /* send out 0s to blank the screen */
SPDR = 0;
while (!(SPSR & 0x80)); }
for (i = 0; i < 6; i++) { /* send out digits 1..6 */
SPDR = hex_pat [digits [i]];
return 0;

67. The MC68HC68T1 Real-Time Clock with Serial Interface
Features:
- Full clock features -- seconds, minutes, hours (AM/PM), day-of-week, date, month, year,
auto leap year
- 32 bytes general-purpose RAM for saving critical data
- power control functions -- sensing power transition, performing power up and power
down
- burst mode for reading/writing successive addresses in clock/RAM
- selectable crystal or 50/60 Hz line input frequency
- clock registers utilize BCD data
- watchdog circuit similar to COP
- battery backup power supply input

68. 68HC68T1 signals
CLK OUT: buffered clock output; 7 selectable
frequencies.
CPUR: CPU reset.
INT: interrupt. Activated when one of the
following occurs:
1. power failure
2. preset alarm time occurs.
3. periodic interrupt
SCK: serial clock for data shifting. Either the
rising or falling edge can be used for data
shifting.
MOSI: master in slave out
MISO: master in slave out
SS: slave select
PSE: power supply enable
POR: power on reset
LINE: line sense.
XTAL IN, XTAL OUT: crystal input/output

69. On-Chip RAM and Registers
- 32 bytes of on-chip RAM and 13 registers
- to access these RAM and registers, the CPU first sends in an 8-bit address and then
performs the actual access
- Each read/writable register and each RAM byte has two addresses: one for read and one
for write
- The address map of these registers and RAM bytes are shown in Figure
- All timer counters and alarm registers are in BCD format (shown in Table 10.5).

71. Clock Control Register
Start/stop: a 1 enables the counter stages of the clock circuitry
Line/XTAL: a 1 selects 50/60 Hz Line input to update the time
XTAL Select: select crystal frequencies.
0 = MHz
1 = MHz
2 = MHz
3 = MHz
50 Hz/60 Hz: A 1 selects 50 Hz for line input. Otherwise, 60 Hz is selected.
CLK OUT2-CLK OUT0: specify one of the seven frequencies to be used as the square wave
output at the CLK OUT pin.
0 = Xtal
1 = Xtal/2
2 = Xtal/4
3 = Xtal/8
4 = disable
5 = 1 Hz
6 = 2 Hz
7 = 50/60 Hz for Line operation, 64 Hz for Xtal operation

72. Interrupt Control Register
Watch dog: When set to 1, the watchdog function is enabled.
Power down: When set to 1, a power down operation is initiated.
Power sense: When set to 1, this bit enables the Line input pin to sense a power failure.
Alarm: When set to 1, the alarm function is enabled. When the alarm time is reached, the
interrupt output is activated
Periodic select: The frequency of the periodic output is selected by these four bits.

74. Status Register
Watchdog. Set to 1 when a CPU failure is detected.
First time up. Set to 1 by a power on reset.
Interrupt true. Set to 1 when one of the three interrupts is valid.
Power sense INT. Set to 1 when the power sense circuit generates an interrupt
Alarm INT. Set to 1 when the contents of the seconds, minutes, and hours time
time counters and alarm latches are equal.
Clock INT. Set to 1 on a periodic interrupt.

75. Interfacing the 68HC68T1 to the 68HC11
- The corresponding pins of the 68HC11
and 68HC68T1 are connected together.
- A battery is added to the 68HC68T1 so
that important information can be kept
when the line power is interrupted.
- An alarm transducer is added and will
be ringing at 4 KHz to remind the user
that the preset alarm time has reached.
- Only the timer function is used.
- A KHz crystal oscillator is used to
generate the clock signal to be used by
the 68HC68T1.
- Data transfer to/from the 68HC68T1 can
occur one byte at a time or in multi-byte
burst mode.
- Each read or write cycle causes
clock/calendar register or RAM address
to automatically increment by 1.

76. Constant definition for the programming of 68HC68T1
regbas equ $1000
SPDR equ $2A
SPCR equ $28
SPSR equ $29
DDRD equ $09
PORTD equ $08
ram_addr equ $80 ; starting address to write the RAM
second_r equ $20 ; read address for seconds
minute_r equ $21 ; read address for minutes
hour_r equ $22 ; read address for hours
day_wk_r equ $23 ; read address for day of week
date_m_r equ $24 ; read address for date of month
month_r equ $25 ; read address for month
year_r equ $26 ; read address for year
stat_reg equ $30 ; read address for status register
clk_ctlr equ $31 ; read address for clock control register
int_ctlr equ $32 ; read address for interrupt control register
second_w equ $A0 ; write address for seconds
minute_w equ $A1 ; write address for minutes
hour_w equ $A2 ; write address for hours
day_wk_w equ $A3 ; write address for day of week

77. date_m_w equ $A4 ; write address for date of month
month_w equ $A5 ; write address for month
year_w equ $A6 ; write address for year
s_alarm equ $A8 ; write address for seconds alarm
m_alarm equ $A9 ; write address for minutes alarm
h_year equ $AA ; write address for hours alarm
clk_ctlw equ $B1 ; write address for clock control register
int_ctlw equ $B2 ; write address for interrupt control register

78. The initialization of the SPI function
- Configure pins SS, CLK, MOSI, TxD for output and MISO and RxD for input. Write
the value % into the DDRD register.
- Choose the following SPI operating parameters:
1. disable SPI interrupt
2. enable SPI function
3. port D normal CMOS pins
4. master mode
5. rising edge of CLK for shifting data
6. 1 Mbits/sec data shifting rate
Write the value $50 into the SPCR register.
The instruction sequence to initialization the SPI system:
ldx #regbas
ldaa #$3A
staa DDRD,X
ldaa #$50
staa SPCR,X

79. Data transfer to and from the 68HC68T1
- Set the SS signal to high during the data transfer process.
- Send the time of day information (7 bytes) and alarm information (3 bytes) in two separate
burst mode transfer because these two blocks of information are not in contiguous addresses.
- Reserve 10 bytes in SRAM of the 68HC11 to hold time-of-day and alarm information.
* The following instruction sequence sends the time-of-day information to the 68HC68T1
org $00
clk_mgt rmb 10 ; block of memory to store time-of-day and alarm information
org $C000
ldx #regbas
bset PORTD,X $20 ; enable data transfer to the 68HC68T1
ldaa #second_w
staa SPDR,X ; send the write address of seconds to the 68HC68T1
brclr SPSR,X $80 * ; wait until the byte is shifted out
ldab #7 ; use accumulator B as the loop count
ldy #clk_mgt ; Y points to the base address of time-of-day information
LP1 ldaa 0,Y
staa SPDR,X ; send out one byte information to the 68HC68T1
iny
decb
bne LP1
bclr PORTD,X $20 ; disable SPI transfer to the 68HC68T1

80. * The following instruction sequence sends out the alarm information to the 68HC68T1
bset PORTD,X $20 ; enable SPI transfer to the 68HC68T1
ldaa #s_alarm
staa SPDR,X ; send out seconds alarm address
brclr SPSR,X $80 * ; wait until the address has been shifted out
ldab #3 ; use accumulator B as the loop count
ldy #clk_mgt+7 ; Y points to the alarm information block
LP2 ldaa 0,Y
staa SPDR,X ; send out one byte of alarm information
brclr SPSR,X $80 * ; wait until the byte is shifted out
iny ; move to the next byte
decb ; decrement the loop count
bne LP2
bclr PORTD,X $20 ; disable SPI transfer to the 68HC68T1
* The following instruction sequence reads the status register of the 68HC68T1
bset PORTD,X $20 ; enable data transfer from the 68HC68T1
ldaa #stat_reg
staa SPDR,X ; send out the address of the status register
brclr SPSR,X $80 * ; wait until the address byte is shifted out
staa SPDR,X ; start an SPI transfer to read the status register
brclr SPSR,X $80 * ; wait until the status register is shifted in
ldaa SPDR,X ; place the status register in accumulator A

81. Clock/Calendar portion
- consists of a long string of counters that are toggled by a 1-Hz input that can be derived
from one of the three sources:
1. an external crystal oscillator applied between pins XTAL IN and XTAL OUT
2. an external frequency source applied to XTAL IN
3. a 50- or 60-Hz source connected to the LINE input
- an AM/PM indicator is available; once set, it toggles at 12:00 AM and 12:00 PM.

82. Alarm operation
- the alarm latches consist of seconds, minutes, and hours registers.
- when the contents of alarm latches equal the values of the seconds, minutes, and hours
time counters, an interrupt is generated.
- the CLK OUT can be used to drive an alarm transducer.
- the procedure for using the alarm function is as follows:
1. disable CLK OUT when the alarm time has not been reached.
2. enable the alarm interrupt.
3. when the alarm time is reached, the alarm interrupt-service routine enables a pulse
output from the CLK OUT pin for some specific amount of time.
- the alarm interrupt should be enabled and its procedure is:
1. enable the periodic interrupt of the 68HC68T1
2. set up the alarm time and then set up the alarm counter. The alarm counter is used
to keep track of the amount of time that the alarm transducer has been turned on.
3. stay in a wait loop while checking if the alarm counter has been decremented to 0.
If yes, turn off the alarm and reinitialize the alarm counter.

83. Alarm interrupt service routine
1. checks the cause of the interrupt by reading the status register
2. returns if the interrupt is periodic and the alarm is not turned on.
3. turns on the alarm transducer if the interrupt is caused by the alarm function.
4. decrement the alarm count by 1 and then returns if the interrupt is caused by periodic
interrupt and the alarm transducer is on.
The interrupt control register should be set up as follows for this application:
- disable watchdog interrupt (clear bit 7)
- disable power down (clear bit 6)
- disable power sense (clear bit 5)
- enable alarm interrupt (set bit 4 to 1)
- set the periodic interrupt frequency to be 1 Hz (set bits 3-0 to 1100)
The value % should be written into the interrupt control register.

84. The clock control and interrupt control registers can be initialized by using the burst mode:
ldx #regbas
bset PORTD,X $20 ; enable data transfer to the 68HC68T1
ldaa #clk_ctlw
staa SPDR,X ; send the write address of the clock control register
brclr SPSR,X $80 * ; wait until the address is shifted out
ldaa #$B4 ; disable CLK OUT when alarm time has not reached
staa SPDR,X ; send out the clock control byte
first_bt brclr SPSR,X $80 first_bt ; wait until the clock control byte is shifted out
ldaa #$1C
staa SPDR,X ; send out the interrupt control byte
sec_bt brclr SPSR,X $80 sec_bt ; wait until the interrupt control byte is shifted out
bclr PORTD,X $20 ; disable data transfer to the 68HC68T1
A flag is needed to indicate whether the alarm transducer has been turned on. The alarm
counter and the alarm flag can be set up as follows:
threemin equ 180 ; let the alarm transducer be turned on for three minutes
alarmcnt rmb 1 ; memory location to store the alarm count
alarmflg rmb 1 ; memory location used as alarm flag
set_alct ldaa #threemin
staa alarmcnt ; initialize alarm count to 180
clr alarmflg ; clear the alarm flag

85. Clock interrupt service routine
clk_ISR ldx #regbas
bset PORTD,X $20 ; enable SPI transfer to the 68HC68T1
ldaa #stat_reg
staa SPDR,X
brclr SPSR,X $80 * ; wait until the address has been shifted out
staa SPDR,X ; trigger an SPI transfer to read the status register
brclr SPSR,X $80 * ; wait until the status register has been shifted in
bclr PORTD,X $20 ; disable SPI transfer
bset PORTD,X $20 ; re-enable SPI transfer so that new address can be sent out
ldaa SPDR,X ; place the status register in A
anda #$02 ; check the alarm interrupt bit
beq periodic ; if interrupt is periodic go and check if the alarm flag is set
ldaa #clk_ctlw ; send out the write address of the clock control register
staa SPDR,X ; “
ldaa #% ; send a new control byte to the clock control register to turn
staa SPDR,X ; on CLK OUT
brclr SPSR,X $80 * ; wait until the new control byte is shifted out
ldaa #1
staa alarmflg ; set the alarm flag
bra exit ; prepare to return from interrupt

86. periodic ldaa alarmflg ; check the alarm flag
beq exit ; return if the alarm is not turned on
dec alarmcnt ; decrement the alarm count if the alarm has been turned on
bne exit ; if alarm is not zero then return
* disable CLK OUT, reinitialize the alarm count and clear the alarm flag when alarm count
* has been decremented to 0
ldaa #threemin
staa alarmcnt
clr alarmflg ; clear the alarm flag
* To disable CLK OUT, write the value % into the clock control register
ldaa #clk_ctlw
staa SPDR,X ; send the write address to the 68HC68T1
brclr SPSR,X $80 * ; wait until the address has been shifted out
ldaa #$B4
staa SPDR,X ; send out the new clock control byte
brclr SPSR,X $80 * ; wait until the new clock control byte has been shifted out
exit bclr PORTD,X $20 ; disable SPI transfer to the 68HC68T1
rti

87. Example 10. 6 For the circuit in Figure 10
Example 10.6 For the circuit in Figure 10.37, write a C function to send the current time-
of-day and alarm time information to the 68HC68T1. This function must also enable the
68HC68T1 to generate periodic and alarm interrupt to the 68HC11.
Solution:
#define second_w 0xA0 /* seconds write address */
#define s_alarm 0xA8 /* write address for seconds alarm */
#define ccr_wad /* clock-control register write address */
init_68HC68T1 (char spi_dir, char spr_ctrl, char t_of_d [ ], char alarm, char ccon [ ]) {
int i;
DDRD = spi_dir; /* set up SPI pin diriections */
SPCR = spr_ctrl; /* initialize SPI parameters */
PORTD |= 0x20; /* enable SPI transfer to the 68HC68T1 */
SPDR = second_w; /* send the write address for seconds */
while (!(SPSR & 0x80)); /* wait until the byte is shifted out */
for (i = 0; i < 7; i+) {
SPDR = t_of_d [i]; /* send the current time to 68HC68T1 */
while (!(SPSR & 0x80)); }

88. PORTD &= 0xDF; /* disable SPI transfer so that new address can be sent */
PORTD |= 0x20; /* enable SPI transfer to the 68HC68T1 */
SPDR = s_alarm; /* send the second alarm address to the 68HC68T1 */
while (!(SPSR & 0x80));
for (i = 0; i < 3; i++) {
SPDR = alarm [i]; /* send new alarm time to the 68HC68T1 */ }
PORTD &= 0xDF;
SPDR = ccr_wad; /* send write address of clock control register */
for (i = 0; i < 2; i++) { /* send out clock and interrupt control info. */
SPDR = ccon[i];
while (!(SPSR 0x80));

89. Example 10.7 Write a main program and an interrupt service routine for the 68HC68T1.
The main program sets up the IRQ interrupt vector, calls the function in Example 10.6 to
initialize the 68HC68T1, sets up alarm count, clears alarm flag, and enable the interrupt.
The IRQ interrupt service routine will perform the operations described earlier. This program
is to be run on the EVB, the EVBU, or the CMD-11A8 demo board.
Solution:
#include <hc11.h>
#define stat_reg 0x30 /* read address of the status register */
unsigned char alarm_cnt, alarm_flg;
unsigned char t_of_d [7], alarm [3], ccon [2];
void IRQ_ISR ( );
main ( ) {
alarm_cnt = 180;
alarm_flg = 0; .
/* read the current time-of-day and alarm time here */
ccon[0] = 0xB4; /* clock control byte */
ccon[1] = 0x1C; /* interrupt control byte */
init_68HC68T1 (0x3A, 0x50, t_of_d [ ], alarm [ ], ccon [ ]);

90. *(unsigned char *)0xee = 0x7E; /* set up IRQ interrupt jump vector */
*(void (**)())0xef = IRQ_ISR;
INTR_ON ( ); .
/* do something else */
return 0; }
#pragma interrupt_handler IRQ_ISR ( );
void IRQ_ISR ( ) {
/* read the status register to identify the cause of interrupt */
PORTD |= 0x20; /* enable SPI transfer to the 68HC68T1 */
SPDR = stat_reg; /* send out status register read address */
while (!(SPSR & 0X80));
SPDR = 0x00; /* read the status register */
while (!(SPSR & 0x80));
PORTD &= 0xDF; /* disable SPI transfer */
if (SPDR & 0x20) { /* interrupt is caused by alarm time */
SPDR = ccr_wad; /* send out the clock-control register write address */
SPDR = 0xB3; /* turn on alarm device */

91. while (!(SPSR &0x80));
alarm_flg = 1; /* set this flag to indicate that alarm is turned on */
PORTD &= 0xDF; /* disable SPI transfer to 68HC68T1 */
return; }
if (!alarm_flg)
return; /* interrupt is caused by periodic interrupt and alarm is not on */
-- alarm_cnt;
if (alarm_cnt)
else {
alarm_cnt = 180;
alarm_flg = 0;
PORTD |= 0x20;
SPDR = clk_ctlw; /* send clock-control register write address */
while (!(SPSR & 0X80));
SPDR = 0xB4; /* turn off alarm */
while (!(SPSR & 0x80));
PORTD &= 0xDF;

92. Other functions of the 68HC68T1 chip
1. Power sensing:
- the voltage level on the LINE input pin is check
- as long as the voltage is either higher or lower than a certain threshold around VDD,
a power failure is indicated.
- the 68HC68T1 may interrupt the CPU on a power failure for the CPU to take
appropriate actions
2. Power-down:
- power down is initiated by the processor
- signals PSE, CLK OUT, and CPUR output will be placed low during a power-down
- procedure of power down is as follows:
a. set the power sense operation (set bit 5 of the interrupt control register)
b. when interrupt occurs, the processor reads the status register to determine the interrupt
source.
c. if a power failure is sensed, the processor does the necessary housekeeping to prepare
for shutdown.
d. the CPU reads the status register again after several milliseconds to determine the
validity of the power failure.
e. the CPU sets power down and disable all interrupts when the power failure is verified.
f. when the power returns and Vsys rises above Vbatt + 0.7V, power up is initiated. The
CPU reset is released and serial communication is established.

93. 3. Power-up
- Power-up is started when the signal POR goes high
- If the Vsys input also goes high, then 68HC68T1 initiates the power-up operation by placing
PSE, CLK OUT, and CPUR to high so that the CPU can start to boot.
4. Watchdog function
- when enabled, the SS pin must be toggled at regular intervals without a serial transfer.
- if the SS pin is not toggled, the 68HC68T1 supplies a CPU reset pulse at the CPUR pin
and the watchdog bit in the status register is set to 1.
- the watchdog service time and CPU reset period (CPUR low) is listed in Table 9.8.