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Published byJackson Jarvis Modified over 3 years ago

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Fuding Ge: Die Area Estimation 1 Resistor Area Where R is the desired resistance R s is the applicable sheet resistance W R is the width of the resistor and S R is the spacing between adjacent resistor stripes.

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Fuding Ge: Die Area Estimation 2 Capacitor Area

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Fuding Ge: Die Area Estimation 3 MOS Transistor W g is the width of the gate, L g is the length of the gate. S gg is the space between adjacent gate stripes of a multi- finger transistor. If transistor need guard rings or separate well, its area will be larger than this estimation.

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Fuding Ge: Die Area Estimation 4 MOS Power Transistor R P : package resistance (including bondwire and leadframe) R ds(on) : on resistance of the MOS power transistor R sp :measured specific on-resistance

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Fuding Ge: Die Area Estimation 5 Cell Area P f is the packing factor and is about 1.5 to 2.0 for CMOS technology.

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Fuding Ge: Die Area Estimation 6 Core Area R f is the routing factor, which accounts for the area consumed by top-level wiring, in the range of 1.0 to 1.5..

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Fuding Ge: Die Area Estimation 7 Die Area Scribe width W scribe : typically 75 to 125 m. Padring width: typically 130% of the bondpad

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Fuding Ge: Die Area Estimation 8 Die Area Factors Three factors: Circuitry it contains (CORE) Pads around its periphery (PADRING) Scribe streets separating it from adjacent dice. Core limited or Pad limited ?

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Fuding Ge: Die Area Estimation 9 Die Perimeter The minimum die perimeter P min required to place the pads: S pad is the minimum spacing allowed between adjacent pads. L corner minimum allowed distance from the die corner to the nearest bondpads.

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Fuding Ge: Die Area Estimation 10 Perimeter Utilization Factor P<1: core-limited; P>1: pad-limited. The the total die area with a square aspect ratio:

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