Presentation on theme: "7-things that we should know about Op-amp Design"— Presentation transcript:
17-things that we should know about Op-amp Design 3/27/20177-things that we should know about Op-amp DesignNatsem India Design’s Pvt. Ltd.
2T. Srinivas 7-things that we should know about Op-amp Design 3/27/20177-things that we should know about Op-amp DesignT. SrinivasStaff EngineerData Converters Group.2
3Objective Op-amp is a fundamental part of Analog Circuit Design. 3/27/2017ObjectiveOp-amp is a fundamental part of Analog Circuit Design.Our aim is to increase your familiarity with Op-amp Design and…Fear of Op-ampIn Analog Circuit Design CourseDesign Systems
4Contents 1. Small Signal Model of MOSFET. 2. Current Mirrors. 3. 3/27/2017Contents1.Small Signal Model of MOSFET.2.Current Mirrors.3.Gain Bandwidth Product of an Op-amp.4.Stability of an Op-amp.5.Slew-rate of an Op-amp.6.Offset of an Op-amp.7.Noise of an Op-amp.Conclusion
51. Small Signal Model of MOSFET. 3/27/20171. Small Signal Model of MOSFET.DSGTriode Region:Saturation Region:VGS1VGS2=VGS1+0.1VGS3=VGS2+0.1
61. Small Signal Model of MOSFET. 3/27/20171. Small Signal Model of MOSFET.Regions of OperationStrong inversionVGS> VTHWeak inversionVGS < VTHTriode regionVDS < VGS -VTHSaturationVDS > VGS -VTH
71. Small Signal Model of MOSFET. 3/27/20171. Small Signal Model of MOSFET.DSGTriode Region:Saturation Region:DSGVinVDCVGS=VDC+VinFor Designing Amplifiers, MOSFET Operating in Saturation Region is preferred [IDS depends on Input!].To achieve -100dB THD Vin < (VGS- VTH)*40mV.The small signal model that we show is valid for MOSFET in Saturation Region and for Vin<< VDSAT.
81. Small Signal Model of MOSFET. 3/27/20171. Small Signal Model of MOSFET.VDS = VDD – IDS*RDSGVDCRVDDVDC + vinVDS = VDD – IDS*R – Iin*RRgm*Vinvout= - gm*vin*RGSDvinCGSrdsEffThis signal model is sufficient for first-cut hand calculations.
91. Small Signal Model of MOSFET. 3/27/20171. Small Signal Model of MOSFET.Intrinsic GainrDsgm*Vinvout= - gm*vin*rDSGSDvinDSGTo Increase Gain reduce VDSAT or increase length of MOSFET.
101. Small Signal Model of MOSFET. 3/27/20171. Small Signal Model of MOSFET.Intrinsic BandwidthCGSrDsgm*VinGSDvinIinIoutTo Increase Bandwidth increase VDSAT or decrease the length of MOSFET.Gain-Speed Product =
111. Small Signal Model of MOSFET. 3/27/20171. Small Signal Model of MOSFET.L=1.5umL=0.5umL=1.0umL=1.0umL=1.5umL=0.5umL=0.5umL=1.0umL=1.5um
121. Small Signal Model of MOSFET. 3/27/20171. Small Signal Model of MOSFET.Example 1:GrDS1gm1*VinSvinrDS2gm2*0VDDVinVDCVOUTM1M2DC GainAC Gain
133/27/20172. Current Mirrors.These are the Basic Building Blocks of Analog IC design.Not Again. It doesn’t make any sense.M2VDD10uAVOUTM1gDS1=1e-6 S & gDS2=0;1uA9uA1VVDD10uAVOUTM2M1Let (W/L)1=(W/L)2 VT=0.8V, gDS=010uA0uA0V10uA1V0uAVOUT = 1.0V IDS2 = 10uAVOUT = 0.2V IDS2 = 10uAVOUT = 0.1V IDS2 = 7.5uAVOUT = 0.0V IDS2 = 0VOUT = 1.0V IDS2 = 9uAVOUT = 0.2V IDS2 = 9uAVOUT = 0.1V IDS2 = 6.75uAVOUT = 0.0V IDS2 = 0Let (W/L)2=2*(W/L)1VOUT = 1.0V IDS2 = 20uAIf gDS1 = gDS2 =1e-6;IOUT=10uA VOUT= ???VOUT=2V IOUT=???
142. Current Mirrors. Small Signal Analysis vin rIN rOUT rIN rOUT 3/27/20172. Current Mirrors.Small Signal AnalysisGrDS1SvinrDS2rINVOUTrOUTVDD10uAVOUTM2M1rINrOUTgm1*Vingm2*Vin= 0Due to CGS we have a Pole Heregm2*Vingm1*VinGrDS1SvinrDS2VOUTCGS1CGS2
152. Current Mirrors. Better Current Mirror à Large Output resistance. 3/27/20172. Current Mirrors.Better Current Mirror à Large Output resistance.VDDVOUTM1M2M3M4V1V2M1 – M3 is the Current Mirror.M4 – M2 helps in achieving high resistance.Requires high turn on voltage. VOUT > V1+VDSAT2V1=VGS3V2=VGS3 + VGS4VDDM1 – M3 is the Current Mirror.M4 – M2 helps in achieving high resistance.VOUT > V3 + VDSAT2 > 2*VDSATVOUTM1M2M3M4M5I1V1V2V3V1=VGS3V2=VGS5V3=V2 – VGS4 > VDSAT
162. Current Mirrors. Wide Swing Current Mirror. 3/27/20172. Current Mirrors.VDDVOUTM1M2M3M4M5I1V1V2V3Wide Swing Current Mirror.There are Two Questions that we should answer.How should we generate V2.We know V3 = a VDSAT, what is the exact value of ‘a’.If M1 – M4 are of same size, for a = 1.25, (W/L)5 = 1/5 (W/L).1/5 (W/L)W/La = 1.5 is fine
172. Current Mirrors. Example 2: If gm=100*gDS Gain = 50. 3/27/20172. Current Mirrors.Example 2:VDDVinVOUTM1M2M3If gm=100*gDS Gain = 50.Gain varies with Process.VDDVinVOUTM1M2If (W/L)2=(W/L)1 Gain = 3.Gain varies with Process.VDCRVDDVinVOUTReplace the R with MOSFET and Build anAmplifier with Gain = 50Amplifier with Gain of 3 (Kn=3*Kp).
182. Current Mirrors. Example 3: (a) (b) VOUT will near to VDD 3/27/20172. Current Mirrors.Example 3:(a)(b)VDDVDDM2 (W/L)=2M3 (W/L)=1M4 (W/L)=110uA20uA150uAM1 (W/L)=???MB1 (W/L)M2 2*(W/L)10uAVOUT = ?MB1 (W/L)M1 (W/L)VGS4 + VGS3 = VGS2 + VGS1(W/L)1 = 15.The above loop formed by Gate-Source voltages is known as Trans-linear loop.VOUT will near to VDDM2 in Triode regionM1 in Saturation Region
193. Gain Bandwidth Product of an Op-amp. 3/27/20173. Gain Bandwidth Product of an Op-amp.1st order Low Pass Filtermag(VOUT)RCVINVOUTPhase (VOUT)VINVOUT
203. Gain Bandwidth Product of an Op-amp. 3/27/20173. Gain Bandwidth Product of an Op-amp.Op-amp in Feed-back.+-VINVOUTAmplifier GBW required to settle in the given time (Ts) and with in given error (e).
213. Gain Bandwidth Product of an Op-amp. 3/27/20173. Gain Bandwidth Product of an Op-amp.Example 4:+-VINVOUTDesign a Amplifier with Gain of 4, operating at 100MHz and it should settle with 10-bit accuracy for a full-scale output of 1V.
223/27/20174. Stability of an Op-amp.I Designed an Oscillator.Phase Margin is not enough.Poles are not in the right location.Lets Change some W/L’s and see.VIN = 1VVOUTWe use simple design technique to deal with stability issues.This approach is sufficient to deal with most of the circuits and systems.
234. Stability of an Op-amp. Two-Stage Amplifier gmi. vIN gdsi sC1 3/27/20174. Stability of an Op-amp.Two-Stage Amplifiergmi. vINgdsisC1gmo. v1gdsosCLv1sCCVOUTvINPolesVDDM1M2M3M4M5I1I2VOUTCCCLDVDV*gm5DVOUT=0DVOUTVNVP
244. Stability of an Op-amp. Two-Stage Amplifier b 3/27/20174. Stability of an Op-amp.Two-Stage AmplifierVINbVOUTVPVNOp-amp in Feedback should be stable.
253/27/20174. Stability of an Op-amp.Two-Stage Amplifier- Condition for Maximally flat response.VINbVOUTVPVNEquate it to 2nd order Butterworth equation.To satisfy Assumption, We use the following rule of thumb.
264. Stability of an Op-amp. Example 5: 3/27/20174. Stability of an Op-amp.Example 5:Design a Amplifier with Gain of 2, operating at 1MHz and when 1V input is applied output should settle with in 2V ± 2mV. [A0=1e7]VINbVOUTVPVN
273/27/20175. Slewrate of an Op-amp.VDD = 5VM1M2M3M4M5I1I2VOUTCCCL3V2V3.83V4V2V4VVOUT = 2VVOUT = 3VVIN = 2VVIN = 3V3V1V2V3V2VSlew-rate limitedLinear systemA Slew-rate limited system will cause non-linearity.
283/27/20175. Slewrate of an Op-amp.f1f2Output Stage can supply huge currentVIN = 2VOutput Stage current limitedf1VOUTf2VIN = 2VOften in switched capacitor circuits, output stage current limitation leads to op-amp slewing.In continuous time circuits where we have to drive resistor loads, output stage current limitation leads to non-linearity.
293/27/20175. Slewrate of an Op-amp.Class-AB output stage should be used when driving resistor loads and some switched capacitor circuits.Class-AB input stage can be employed to reduce power.VDD = 5VM1M2M3M4M11I1VOUTCCCLI2M6M5M7M8M9M10M12Two-stage op-amp with class-AB output stageVPVN
303/27/20175. Slewrate of an Op-amp.Design Considerations for Slewrate (Switched capacitor Circuits).TSlewTSettleTCLK/2TCLK
315. Slewrate of an Op-amp. Example 6: 3/27/20175. Slewrate of an Op-amp.VDD = 5VM1M2M3M4I1I2M6M5M7M8Example 6:f1f2VINVOUTCLCSCF2.5VDesign a Amplifier with Gain of 2 for 10-bit ADC, operating at clock frequency of 1MHz with a Maximum input amplitude of 1V. Assume CF=1pF and CL=1pF.
325. Slewrate of an Op-amp. Example 6: CF vOUT v1 CS CP gm*v1 gDS CL vIN 3/27/20175. Slewrate of an Op-amp.Example 6:CLCFCPCSvINvOUTgm*v1gDSv1
333/27/20175. Slewrate of an Op-amp.Example 6:What is this
345. Slewrate of an Op-amp. Example 6: 3/27/20175. Slewrate of an Op-amp.Example 6:Op-amp Can’t supply Infinite current.vINCLCFCPCSvOUTgm*v1gDSv1
355. Slewrate of an Op-amp. Example 7: 3/27/20175. Slewrate of an Op-amp.Example 7:Below op-amp should be designed for a Slewrate of 6V/us, what should be the input stage tail current if the op-amp is folded cascode op-amp.‘VIP, VIN’ forms fully differential signals (2VPP) with ‘VCM’ as common mode.10pFVIP1pFParasitic Caps.VCM=1V1pFVIN10pFMinimum Tail Current = 12uA.
366. Offset of an Op-amp. 1. Systematic Offset: 3/27/20176. Offset of an Op-amp.1. Systematic Offset:Case 1: VDSAT and Length of M3-M4 & M5 are same.Offset=48uVVDD = 5VM1M2M3M4M5VOUTCCCLCase 2: VDSAT of M3-M4 & M5 is same but Length is differentOffset=715uV15u/1.5uCase 3: Length of M3-M4 & M5 is same but VDSAT is differentOffset=718uV10uA10uA10*15u/1.5u40*15u/1.5u10*5u/0.5u5.3u/1.5u2.5V20uA100uA
376. Offset of an Op-amp. 2. Random Offset : Due to Process Variations 3/27/20176. Offset of an Op-amp.2. Random Offset : Due to Process VariationsProcess steps like Photolithography, Etching and Deposition are not uniform.Values of V1,V2, V3 depends on the sigma of the process. Normally they will be in the order of ‘mV’.Proper layout [Common-Centroid Layout, proximity matching] techniques can reduce the mismatch, thus Offset.Can a designer play a role in reducing the over-all Offset.VDD = 5VM1M2M3M4M5VOUTCCM6M7V4V2V5V720uA100uA
386. Offset of an Op-amp. 2. Random Offset : Due to Process Variations 3/27/20176. Offset of an Op-amp.2. Random Offset : Due to Process VariationsInput Referred Offset Due to: VB2 & V5VDD = 5VM1M2M3M4M5VOUTCCM6M720uAV5=(gm7*V7/gm5)VINVIN + V5/A1100uA + gm7*V7100uAV7
396. Offset of an Op-amp. 2. Random Offset : Due to Process Variations 3/27/20176. Offset of an Op-amp.2. Random Offset : Due to Process VariationsInput Referred Offset Due to: V2 & V4VDD = 5VV4M3M410uA + gm4*V4M5VOUTM1M2VINVIN+(gm4/gm2)*V4CC20uAM6M7
406. Offset of an Op-amp. 2. Random Offset : Due to Process Variations 3/27/20176. Offset of an Op-amp.2. Random Offset : Due to Process VariationsDesign M1-M2 (Differential Pair) and M3-M4 (Current Mirror) Carefully.Decrease gm4 (For given ‘I’ Increase VDSAT for Current Mirrors).Increase gm2 (For given ‘I’ Decrease VDSAT for Differential pair).To reduce V2 and V4, use Large devices (Large L and Large W). Mismatch is inversely proportional to the Area of the MOSFET.
417. Noise of an Op-amp. Types of “Noise” Interference Device Noise 3/27/20177. Noise of an Op-amp.Types of “Noise”InterferenceCross talk, Clock Coupling…Supply Noise.Taken Care by proper design (Shielding, Differential circuits, etc…)Device NoiseThermal Noise (Fundamental).Process related (1/f noise).
427. Noise of an Op-amp. Thermal Noise: 3/27/20177. Noise of an Op-amp.Thermal Noise:Dissipative elements (resistors, MOSFET’s, …)Random fluctuations of v(t) of i(t).White noise with zero mean.ResistorMOS Noise (Strong inversion)R*
437. Noise of an Op-amp. kT/C Noise (Resistor): 100nF 1K 100K Case 1: 3/27/20177. Noise of an Op-amp.kT/C Noise (Resistor):100nF1K100KCase 1:Case 2:Total Noise=200nV*RCR
447. Noise of an Op-amp. kT/C Noise (Op-amp): 3/27/20177. Noise of an Op-amp.kT/C Noise (Op-amp):Noise Analysis is Similar to offset AnalysisWe can neglect the noise due to M5 & MBX.Assume gm1=gm2 & gm3=gm4Calculating the input referred noise.VDD = 5VM1M2M3M4M5VOUTCCMB1MB2VPVNin12in22in42in32vn2
457. Noise of an Op-amp. kT/C Noise (Op-amp): 3/27/20177. Noise of an Op-amp.kT/C Noise (Op-amp):For b=1, CC=10pF and gm1=gm3=80uSNoise at the output VoutRMS=32uV.1/f - noise is suppressed by assigning kf=0Output NoiseTotal Noise=40uVvn2bA(s)VoutCaution: RHS Zero is neglect for calculations, for a poor design it will increase the total output - noise drastically.
467. Noise of an Op-amp. 1/f Noise (‘Fake’ Noise): 3/27/20177. Noise of an Op-amp.1/f Noise (‘Fake’ Noise):Caused by traps in semiconductor materialDue to contamination or crystal defectsHas a 1/f power spectral densityFigure of Merit is called ‘Kf’ and Kf=A/ToxB.Kf is process dependent.For TOX>900A, NMOS(Kf) > PMOS(Kf). So PMOS is less noisy.
477. Noise of an Op-amp. 1/f Noise (‘Fake’ Noise): 3/27/20177. Noise of an Op-amp.1/f Noise (‘Fake’ Noise):Kf=1.36e-27, IDS=500uAflo=1Hz, fhi=1MHz, Tox=1250AW/L=140u/1u1VW/LIRMS=40nAW/L=140u/1uW/L=35u/1uW/L=70u/2u
483/27/2017CONCLUSIONI hope the topics covered would be useful as a starting point and help you to extend the concepts to system level issues.I express my gratitude to following people:Inventors of Google.My Professors at IIT Madras.For Natsem India and RVCE.For SANYO Japan.
493/27/2017About AuthorArea of Interest: Analog/Mixed-signal Integrated Circuit Design, with focus on SD Data converters.Education: M.Tech, Microelectronics and VLSI Design, IIT Madras, Chennai, B.Tech, Electronics & Communications, S.V University, Tirupati, 1999.Work Experience Associated with SANYO LSI, India (Feb ‘01 - April ‘05). Associated with Natsem, India (May ‘05 - Present).Design Experience: Multi-stage rail-to-rail operational amplifiers, Switched capacitor Circuits. Architectures for 20-bit/24-bit ADC/DAC.