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**7-things that we should know about Op-amp Design**

3/27/2017 7-things that we should know about Op-amp Design Natsem India Design’s Pvt. Ltd.

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**T. Srinivas 7-things that we should know about Op-amp Design**

3/27/2017 7-things that we should know about Op-amp Design T. Srinivas Staff Engineer Data Converters Group. 2

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**Objective Op-amp is a fundamental part of Analog Circuit Design.**

3/27/2017 Objective Op-amp is a fundamental part of Analog Circuit Design. Our aim is to increase your familiarity with Op-amp Design and… Fear of Op-amp In Analog Circuit Design Course Design Systems

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**Contents 1. Small Signal Model of MOSFET. 2. Current Mirrors. 3.**

3/27/2017 Contents 1. Small Signal Model of MOSFET. 2. Current Mirrors. 3. Gain Bandwidth Product of an Op-amp. 4. Stability of an Op-amp. 5. Slew-rate of an Op-amp. 6. Offset of an Op-amp. 7. Noise of an Op-amp. Conclusion

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**1. Small Signal Model of MOSFET.**

3/27/2017 1. Small Signal Model of MOSFET. D S G Triode Region: Saturation Region: VGS1 VGS2=VGS1+0.1 VGS3=VGS2+0.1

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**1. Small Signal Model of MOSFET.**

3/27/2017 1. Small Signal Model of MOSFET. Regions of Operation Strong inversion VGS> VTH Weak inversion VGS < VTH Triode region VDS < VGS -VTH Saturation VDS > VGS -VTH

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**1. Small Signal Model of MOSFET.**

3/27/2017 1. Small Signal Model of MOSFET. D S G Triode Region: Saturation Region: D S G Vin VDC VGS=VDC+Vin For Designing Amplifiers, MOSFET Operating in Saturation Region is preferred [IDS depends on Input!]. To achieve -100dB THD Vin < (VGS- VTH)*40mV. The small signal model that we show is valid for MOSFET in Saturation Region and for Vin<< VDSAT.

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**1. Small Signal Model of MOSFET.**

3/27/2017 1. Small Signal Model of MOSFET. VDS = VDD – IDS*R D S G VDC R VDD VDC + vin VDS = VDD – IDS*R – Iin*R R gm*Vin vout= - gm*vin*R G S D vin CGS rds Eff This signal model is sufficient for first-cut hand calculations.

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**1. Small Signal Model of MOSFET.**

3/27/2017 1. Small Signal Model of MOSFET. Intrinsic Gain rDs gm*Vin vout= - gm*vin*rDS G S D vin D S G To Increase Gain reduce VDSAT or increase length of MOSFET.

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**1. Small Signal Model of MOSFET.**

3/27/2017 1. Small Signal Model of MOSFET. Intrinsic Bandwidth CGS rDs gm*Vin G S D vin Iin Iout To Increase Bandwidth increase VDSAT or decrease the length of MOSFET. Gain-Speed Product =

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**1. Small Signal Model of MOSFET.**

3/27/2017 1. Small Signal Model of MOSFET. L=1.5um L=0.5um L=1.0um L=1.0um L=1.5um L=0.5um L=0.5um L=1.0um L=1.5um

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**1. Small Signal Model of MOSFET.**

3/27/2017 1. Small Signal Model of MOSFET. Example 1: G rDS1 gm1*Vin S vin rDS2 gm2*0 VDD Vin VDC VOUT M1 M2 DC Gain AC Gain

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3/27/2017 2. Current Mirrors. These are the Basic Building Blocks of Analog IC design. Not Again. It doesn’t make any sense. M2 VDD 10uA VOUT M1 gDS1=1e-6 S & gDS2=0; 1uA 9uA 1V VDD 10uA VOUT M2 M1 Let (W/L)1=(W/L)2 VT=0.8V, gDS=0 10uA 0uA 0V 10uA 1V 0uA VOUT = 1.0V IDS2 = 10uA VOUT = 0.2V IDS2 = 10uA VOUT = 0.1V IDS2 = 7.5uA VOUT = 0.0V IDS2 = 0 VOUT = 1.0V IDS2 = 9uA VOUT = 0.2V IDS2 = 9uA VOUT = 0.1V IDS2 = 6.75uA VOUT = 0.0V IDS2 = 0 Let (W/L)2=2*(W/L)1 VOUT = 1.0V IDS2 = 20uA If gDS1 = gDS2 =1e-6; IOUT=10uA VOUT= ??? VOUT=2V IOUT=???

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**2. Current Mirrors. Small Signal Analysis vin rIN rOUT rIN rOUT**

3/27/2017 2. Current Mirrors. Small Signal Analysis G rDS1 S vin rDS2 rIN VOUT rOUT VDD 10uA VOUT M2 M1 rIN rOUT gm1*Vin gm2*Vin = 0 Due to CGS we have a Pole Here gm2*Vin gm1*Vin G rDS1 S vin rDS2 VOUT CGS1 CGS2

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**2. Current Mirrors. Better Current Mirror à Large Output resistance.**

3/27/2017 2. Current Mirrors. Better Current Mirror à Large Output resistance. VDD VOUT M1 M2 M3 M4 V1 V2 M1 – M3 is the Current Mirror. M4 – M2 helps in achieving high resistance. Requires high turn on voltage. VOUT > V1+VDSAT2 V1=VGS3 V2=VGS3 + VGS4 VDD M1 – M3 is the Current Mirror. M4 – M2 helps in achieving high resistance. VOUT > V3 + VDSAT2 > 2*VDSAT VOUT M1 M2 M3 M4 M5 I1 V1 V2 V3 V1=VGS3 V2=VGS5 V3=V2 – VGS4 > VDSAT

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**2. Current Mirrors. Wide Swing Current Mirror.**

3/27/2017 2. Current Mirrors. VDD VOUT M1 M2 M3 M4 M5 I1 V1 V2 V3 Wide Swing Current Mirror. There are Two Questions that we should answer. How should we generate V2. We know V3 = a VDSAT, what is the exact value of ‘a’. If M1 – M4 are of same size, for a = 1.25, (W/L)5 = 1/5 (W/L). 1/5 (W/L) W/L a = 1.5 is fine

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**2. Current Mirrors. Example 2: If gm=100*gDS Gain = 50.**

3/27/2017 2. Current Mirrors. Example 2: VDD Vin VOUT M1 M2 M3 If gm=100*gDS Gain = 50. Gain varies with Process. VDD Vin VOUT M1 M2 If (W/L)2=(W/L)1 Gain = 3. Gain varies with Process. VDC R VDD Vin VOUT Replace the R with MOSFET and Build an Amplifier with Gain = 50 Amplifier with Gain of 3 (Kn=3*Kp).

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**2. Current Mirrors. Example 3: (a) (b) VOUT will near to VDD**

3/27/2017 2. Current Mirrors. Example 3: (a) (b) VDD VDD M2 (W/L)=2 M3 (W/L)=1 M4 (W/L)=1 10uA 20uA 150uA M1 (W/L)=??? MB1 (W/L) M2 2*(W/L) 10uA VOUT = ? MB1 (W/L) M1 (W/L) VGS4 + VGS3 = VGS2 + VGS1 (W/L)1 = 15. The above loop formed by Gate-Source voltages is known as Trans-linear loop. VOUT will near to VDD M2 in Triode region M1 in Saturation Region

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**3. Gain Bandwidth Product of an Op-amp.**

3/27/2017 3. Gain Bandwidth Product of an Op-amp. 1st order Low Pass Filter mag(VOUT) R C VIN VOUT Phase (VOUT) VIN VOUT

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**3. Gain Bandwidth Product of an Op-amp.**

3/27/2017 3. Gain Bandwidth Product of an Op-amp. Op-amp in Feed-back. + - VIN VOUT Amplifier GBW required to settle in the given time (Ts) and with in given error (e).

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**3. Gain Bandwidth Product of an Op-amp.**

3/27/2017 3. Gain Bandwidth Product of an Op-amp. Example 4: + - VIN VOUT Design a Amplifier with Gain of 4, operating at 100MHz and it should settle with 10-bit accuracy for a full-scale output of 1V.

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3/27/2017 4. Stability of an Op-amp. I Designed an Oscillator. Phase Margin is not enough. Poles are not in the right location. Lets Change some W/L’s and see. VIN = 1V VOUT We use simple design technique to deal with stability issues. This approach is sufficient to deal with most of the circuits and systems.

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**4. Stability of an Op-amp. Two-Stage Amplifier gmi. vIN gdsi sC1**

3/27/2017 4. Stability of an Op-amp. Two-Stage Amplifier gmi. vIN gdsi sC1 gmo. v1 gdso sCL v1 sCC VOUT vIN Poles VDD M1 M2 M3 M4 M5 I1 I2 VOUT CC CL DV DV*gm5 DVOUT=0 DVOUT VN VP

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**4. Stability of an Op-amp. Two-Stage Amplifier b**

3/27/2017 4. Stability of an Op-amp. Two-Stage Amplifier VIN b VOUT VP VN Op-amp in Feedback should be stable.

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3/27/2017 4. Stability of an Op-amp. Two-Stage Amplifier- Condition for Maximally flat response. VIN b VOUT VP VN Equate it to 2nd order Butterworth equation. To satisfy Assumption, We use the following rule of thumb.

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**4. Stability of an Op-amp. Example 5:**

3/27/2017 4. Stability of an Op-amp. Example 5: Design a Amplifier with Gain of 2, operating at 1MHz and when 1V input is applied output should settle with in 2V ± 2mV. [A0=1e7] VIN b VOUT VP VN

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3/27/2017 5. Slewrate of an Op-amp. VDD = 5V M1 M2 M3 M4 M5 I1 I2 VOUT CC CL 3V 2V 3.8 3V 4V 2V 4V VOUT = 2V VOUT = 3V VIN = 2V VIN = 3V 3V 1V 2V 3V 2V Slew-rate limited Linear system A Slew-rate limited system will cause non-linearity.

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3/27/2017 5. Slewrate of an Op-amp. f1 f2 Output Stage can supply huge current VIN = 2V Output Stage current limited f1 VOUT f2 VIN = 2V Often in switched capacitor circuits, output stage current limitation leads to op-amp slewing. In continuous time circuits where we have to drive resistor loads, output stage current limitation leads to non-linearity.

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3/27/2017 5. Slewrate of an Op-amp. Class-AB output stage should be used when driving resistor loads and some switched capacitor circuits. Class-AB input stage can be employed to reduce power. VDD = 5V M1 M2 M3 M4 M11 I1 VOUT CC CL I2 M6 M5 M7 M8 M9 M10 M12 Two-stage op-amp with class-AB output stage VP VN

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3/27/2017 5. Slewrate of an Op-amp. Design Considerations for Slewrate (Switched capacitor Circuits). TSlew TSettle TCLK/2 TCLK

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**5. Slewrate of an Op-amp. Example 6:**

3/27/2017 5. Slewrate of an Op-amp. VDD = 5V M1 M2 M3 M4 I1 I2 M6 M5 M7 M8 Example 6: f1 f2 VIN VOUT CL CS CF 2.5V Design a Amplifier with Gain of 2 for 10-bit ADC, operating at clock frequency of 1MHz with a Maximum input amplitude of 1V. Assume CF=1pF and CL=1pF.

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**5. Slewrate of an Op-amp. Example 6: CF vOUT v1 CS CP gm*v1 gDS CL vIN**

3/27/2017 5. Slewrate of an Op-amp. Example 6: CL CF CP CS vIN vOUT gm*v1 gDS v1

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3/27/2017 5. Slewrate of an Op-amp. Example 6: What is this

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**5. Slewrate of an Op-amp. Example 6:**

3/27/2017 5. Slewrate of an Op-amp. Example 6: Op-amp Can’t supply Infinite current. vIN CL CF CP CS vOUT gm*v1 gDS v1

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**5. Slewrate of an Op-amp. Example 7:**

3/27/2017 5. Slewrate of an Op-amp. Example 7: Below op-amp should be designed for a Slewrate of 6V/us, what should be the input stage tail current if the op-amp is folded cascode op-amp. ‘VIP, VIN’ forms fully differential signals (2VPP) with ‘VCM’ as common mode. 10pF VIP 1pF Parasitic Caps. VCM=1V 1pF VIN 10pF Minimum Tail Current = 12uA.

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**6. Offset of an Op-amp. 1. Systematic Offset:**

3/27/2017 6. Offset of an Op-amp. 1. Systematic Offset: Case 1: VDSAT and Length of M3-M4 & M5 are same. Offset=48uV VDD = 5V M1 M2 M3 M4 M5 VOUT CC CL Case 2: VDSAT of M3-M4 & M5 is same but Length is different Offset=715uV 15u/1.5u Case 3: Length of M3-M4 & M5 is same but VDSAT is different Offset=718uV 10uA 10uA 10*15u/1.5u 40*15u/1.5u 10*5u/0.5u 5.3u/1.5u 2.5V 20uA 100uA

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**6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations**

3/27/2017 6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations Process steps like Photolithography, Etching and Deposition are not uniform. Values of V1,V2, V3 depends on the sigma of the process. Normally they will be in the order of ‘mV’. Proper layout [Common-Centroid Layout, proximity matching] techniques can reduce the mismatch, thus Offset. Can a designer play a role in reducing the over-all Offset. VDD = 5V M1 M2 M3 M4 M5 VOUT CC M6 M7 V4 V2 V5 V7 20uA 100uA

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**6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations**

3/27/2017 6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations Input Referred Offset Due to: VB2 & V5 VDD = 5V M1 M2 M3 M4 M5 VOUT CC M6 M7 20uA V5=(gm7*V7/gm5) VIN VIN + V5/A1 100uA + gm7*V7 100uA V7

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**6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations**

3/27/2017 6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations Input Referred Offset Due to: V2 & V4 VDD = 5V V4 M3 M4 10uA + gm4*V4 M5 VOUT M1 M2 VIN VIN+(gm4/gm2)*V4 CC 20uA M6 M7

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**6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations**

3/27/2017 6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations Design M1-M2 (Differential Pair) and M3-M4 (Current Mirror) Carefully. Decrease gm4 (For given ‘I’ Increase VDSAT for Current Mirrors). Increase gm2 (For given ‘I’ Decrease VDSAT for Differential pair). To reduce V2 and V4, use Large devices (Large L and Large W). Mismatch is inversely proportional to the Area of the MOSFET.

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**7. Noise of an Op-amp. Types of “Noise” Interference Device Noise**

3/27/2017 7. Noise of an Op-amp. Types of “Noise” Interference Cross talk, Clock Coupling… Supply Noise. Taken Care by proper design (Shielding, Differential circuits, etc…) Device Noise Thermal Noise (Fundamental). Process related (1/f noise).

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**7. Noise of an Op-amp. Thermal Noise:**

3/27/2017 7. Noise of an Op-amp. Thermal Noise: Dissipative elements (resistors, MOSFET’s, …) Random fluctuations of v(t) of i(t). White noise with zero mean. Resistor MOS Noise (Strong inversion) R *

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**7. Noise of an Op-amp. kT/C Noise (Resistor): 100nF 1K 100K Case 1:**

3/27/2017 7. Noise of an Op-amp. kT/C Noise (Resistor): 100nF 1K 100K Case 1: Case 2: Total Noise=200nV * R C R

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**7. Noise of an Op-amp. kT/C Noise (Op-amp):**

3/27/2017 7. Noise of an Op-amp. kT/C Noise (Op-amp): Noise Analysis is Similar to offset Analysis We can neglect the noise due to M5 & MBX. Assume gm1=gm2 & gm3=gm4 Calculating the input referred noise. VDD = 5V M1 M2 M3 M4 M5 VOUT CC MB1 MB2 VP VN in12 in22 in42 in32 vn2

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**7. Noise of an Op-amp. kT/C Noise (Op-amp):**

3/27/2017 7. Noise of an Op-amp. kT/C Noise (Op-amp): For b=1, CC=10pF and gm1=gm3=80uS Noise at the output VoutRMS=32uV. 1/f - noise is suppressed by assigning kf=0 Output Noise Total Noise=40uV vn2 b A(s) Vout Caution: RHS Zero is neglect for calculations, for a poor design it will increase the total output - noise drastically.

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**7. Noise of an Op-amp. 1/f Noise (‘Fake’ Noise):**

3/27/2017 7. Noise of an Op-amp. 1/f Noise (‘Fake’ Noise): Caused by traps in semiconductor material Due to contamination or crystal defects Has a 1/f power spectral density Figure of Merit is called ‘Kf’ and Kf=A/ToxB. Kf is process dependent. For TOX>900A, NMOS(Kf) > PMOS(Kf). So PMOS is less noisy.

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**7. Noise of an Op-amp. 1/f Noise (‘Fake’ Noise):**

3/27/2017 7. Noise of an Op-amp. 1/f Noise (‘Fake’ Noise): Kf=1.36e-27, IDS=500uA flo=1Hz, fhi=1MHz, Tox=1250A W/L=140u/1u 1V W/L IRMS=40nA W/L=140u/1u W/L=35u/1u W/L=70u/2u

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3/27/2017 CONCLUSION I hope the topics covered would be useful as a starting point and help you to extend the concepts to system level issues. I express my gratitude to following people: Inventors of Google. My Professors at IIT Madras. For Natsem India and RVCE. For SANYO Japan.

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3/27/2017 About Author Area of Interest: Analog/Mixed-signal Integrated Circuit Design, with focus on SD Data converters. Education: M.Tech, Microelectronics and VLSI Design, IIT Madras, Chennai, B.Tech, Electronics & Communications, S.V University, Tirupati, 1999. Work Experience Associated with SANYO LSI, India (Feb ‘01 - April ‘05). Associated with Natsem, India (May ‘05 - Present). Design Experience: Multi-stage rail-to-rail operational amplifiers, Switched capacitor Circuits. Architectures for 20-bit/24-bit ADC/DAC.

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