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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 1 Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [LDPC for TFI-OFDM PHY] Date Submitted: [September 2003] Source: [Yaron Rashi, Eran Sharon, Prof. Simon Litsyn] Company [Infineon Technologies] Address [P.O.Box 8631, Poleg Industrial Area, Netanya 42504, Israel] Voice:[ ], FAX: [ ], Re: [] Abstract:[comparison between LDPC and Convolution error correction codes for the TFI-OFDM PHY] Purpose:[Propose an efficient error correction layer] Notice:This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release:The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 2 LDPC Efficient Alternative FEC for the TFI-OFDM PHY proposal

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 3 LDPC Introduction Discovered by Gallager(1963), rediscovered later by Neal & Mackay (MN codes) and by Sipser & Spielman (Expander codes) State of the art codes that exhibit Near Shannon limit performance. Practical - Simple decoding algorithms based on Message-Passing decoding: – Low decoding complexity – allow parallel implementation – enabling high data rates Flexibility in choice of parameters and amenability to rigorous analysis and design make it possible to design appropriate LDPC codes for many communication scenarios. Adopted in DVB. Considered for adoption in IEEE

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 4 LDPC Introduction (cont.) H n n-k Parity-Check Matrix A regular (dv,dc)-LDPC code is a linear block code represented by a sparse parity-check matrix H, such that each column of H contains a small fixed number dv of 1s and each raw of H contains a small fixed number dc of 1s.

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 5 LDPC Introduction (cont.) Parity Check Nodes d c =6 Variable Nodes d v =3 n n-k The code can also be represented by a bipartite graph such that the left side nodes (variable nodes) represent the codeword bits and the right side nodes (check nodes) represent the parity-check constraints on the codeword bits. dv and dc are the variable and check nodes degree of the regular code. n n-k

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 6 LDPC Introduction (cont.) Regular LDPC codes can be generalized to irregular LDPC codes exhibiting better performance. An irregular LDPC code is represented by an irregular bipartite graph, where the degree of each left and right nodes can be different. The ensemble of irregular LDPC codes is defined by the left and right degree distributions.

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 7 Simulated System Parameters 2 modes were simulated: Info. Data Rate122.2 Mbps480 Mbps Modulation/ConstellationOFDM/QPSK FFT Size128 Coding RateR = 1/3R = 3/4 Duty cycle1/21 Spreading Rate11 Information Tones100 Data Tones100 Info. Length242.4 ns Cyclic Prefix30.3 ns60.6 ns Guard Interval-9.5 ns Symbol Length272.7 ns312.5 ns Channel Bit Rate366.7 Mbps640 Mbps Multi-path Tolerance30.3 ns60.6 ns

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 8 Simulated System Parameters 3 – band simulation: BAND_ID (n b ) Lower Frequency (f l ) Center Frequency (f c ) Higher Frequency (f h ) MHz3432 MHz3696 MHz MHz4224 MHz MHz4752 MHz

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 9 Simulation Link Budget Simulation was done according to the following link budget: Where

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide Mbps System Simulation Convolution code: –Rate 1/3 64-state convolutional code G = [117, 155, 127] 8 –Coded bits interleaved across tones and bands: Interleaving is done across 3 OFDM symbols, each CC output stream is interleaved and mapped to a different band. b 0,0 b 0,1, … b 0,199 b 0,0 b 0,10, … b 0,190 b 0,1 b 0,11 …b 0,191 … b 0,0 b 1,0,b 2,0 … b 0,199 b 1,199 b 2,199 b 1,0 b 1,1, … b 1,199 b 1,0 b 1,10, … b 1,190 b 1,1 b 1,11 …b 1,191 … b 2,0 b 2,1, … b 2,199 b 2,0 b 2,10, … b 2,190 b 2,1 b 2,11 …b 2,191 …

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide Mbps System Simulation LDPC code: –Rate 1/3 LDPC codes with various block length where simulated –Code parameters Left degrees: minimal degree 3, maximal degree 12, average degree 4.18 Right degrees: minimal degree 6, maximal degree 7, average degree 6.27 Code length: – N = 1200 bit (6 OFDM symbols), K = 400 bit (50Byte) – N = 6000 bit (30 OFDM symbols), K = 2000 bit (250Byte) – N = bit (120 OFDM symbols), K = 8000 bit (1000Byte)

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide Mbps System Simulation AWGN channel simulation: –1000 packets for each distance –Packet length: 1000 Byte Capacity = m Capacity = dB

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide Mbps System Simulation UWB channel CM3 simulation (shadowing eliminated) Cycled through all 100 channel realizations, 100 packets are transmitted over each channel realization. Packet length 1000 Byte PER is averaged over 90 best channel realizations

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide Mbps System Simulation Convolution code: –Rate ¾ convolution code derived by puncturing of a rate 1/3 64-state convolution code G = [117, 155, 127] 8 as described in TI PHY layer proposal for IEEE P task group 3a (IEEE P /142r1) –Coded bits interleaved across tones and bands. Interleaving is done across 3 OFDM symbols (details omitted).

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide Mbps System Simulation LDPC code: –Rate 3/4 LDPC codes with various block length where simulated –Code parameters Code 1: N = 1200 bit (6 OFDM symbols), K = 900 bit (112.5Byte) regular (3,12)-LDPC code Code 2: N = 3600 bit (18 OFDM symbols), K = 2700 bit (337.5Byte) irregular LDPC code: left degrees: min 3, max 8, average 3.55 right degrees: min 14, max 15, average 14.2 Code 3: N = bit (54 OFDM symbols), K = 8100 bit (1012.5Byte) irregular LDPC code: left degrees: min 3, max 12, average 4 ; right degree 16

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide Mbps System Simulation AWGN channel simulation: –1000 packets for each distance –Packet length: Byte Capacity = 1.788dB Capacity = 12.45m

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 17 Complexity Convolution code: –Studies showed that the Viterbi core for 480 mbps is feasible in k gates at clock speeds ~132MHz (does that include interleaving) LDPC code: –The same decoder architecture can be used for decoding different rate codes. Each additional code will require an additional ROM for holding the code description. –Implementation of a LDPC decoder for the 480Mbps system will require (Assuming 150Mhz clock) –Encoder complexity is approximately 25% of the decoder complexity Code length RAM [Kbytes]61828 ROM [Kbytes] logic [Kgates]

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doc.: IEEE /0353 Submission September 2003 Yaron Rashi, Infineon TechnologiesSlide 18 To Do –Redesign of the parity check matrix (H) in order to achieve improved robustness to fading and collisions. –Choose the preferred block size (code length) according to complexity-performance trade off.

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