1. Ketan Patel, Igor Markov, John Hayes {knpatel, imarkov, jhayes}@eecs.umich.edu University of Michigan Abstract Circuit reliability is an increasingly important design consideration for modern logic circuits. To this end, our work focuses on the evaluation of circuit reliability under probabilistic gate-level fault models that can capture both soft errors, e.g., radiation-related, and spatially-uniform manufacturing defects. This basic task can, in principle, be used by synthesis procedures to select more reliable circuits to estimate yield for electronic nanotechnologies where high defect density is expected. We propose a matrix-based formalism to compute the error probability of the whole circuit based on probabilities of specific gate errors. This formalism is surprisingly related to that of quantum circuits, but also exhibits several new features. The numerical computation of error probabilities in large circuits runs into the same scalability problems as the simulation of quantum circuits. Therefore, we hope to adapt recent advances in quantum circuit simulation to the context of this work. Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models Component Interconnections Fault-tolerant Circuits Fault-tolerant circuits can be analyzed using our formalism. encoded inputs  columns in probabilistic transfer matrix corresponding to non-codewords eliminated encoded outputs  ideal transfer matrix modified to have multiple ones in each column, corresponding to each of the possible correct outputs Probabilistic Transfer Matrix Probabilistic transfer matrix row indices – represent outputs values column indices – represent inputs values Matrix elements capture pairwise transition probabilities Example: Probabilistic AND gate inputs output 00 01 10 11 0101 probability output is 1 when input is 10 Circuit Example Consider two circuits implementing the function b+ac Gate error probability (p) Output error probability 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Circuit (b) Circuit (a) abcabc acbacb (a)(b) INV OR (AND  AND)’ OR (AND  INV) (INV  INV  I 2 ) Relation to Quantum Simulation Ongoing Work Incorporate into circuit synthesis methods BDD-based methods to counter scalability issues  similar methods have been used for quantum simulation Software for automated circuit reliability analysis Connections to quantum computing Other formalism for evaluating circuit reliability Reliability analysis for special circuits structures The circuit reliability can be determined from its probabilistic transfer matrix: The probabilistic transfer matrix for a circuit can be determined from those of its gates, using operations corresponding to three basic methods of composition: serial, parallel and fanout connections. ABAB A B Parallel Connection A B Serial Connection BA Motivation Current fault models don’t address transient failures  Need probabilistic fault models Circuit reliability depends not only on faultiness of gates but also on circuit structure  Need method to incorporate circuit structure Probabilistic Fault Model Assume gates gives an incorrect output with some probability. Example: Probabilistic AND gate B’ is the prob. transfer matrix of component B with columns corresponding to invalid inputs removed. 0000 0 with probability 1-p 1 with probability p ideal transfer matrix (I.e., no errors) circuit input probabilities (j,i)-th entry of probabilistic transfer matrix circuit error probability Quantum simulationOur formalism No fanoutFanout Square matricesRectangular matrices Complex, unitary matrices Real matrices Final step: measurement Final step: error probability calculation Quantum simulationOur formalism Gate operations Represented by matrices Serial connections Represented by matrix product Parallel connections Represented by tensor product Matrix sizeDoubly exponential Similarities Differences AB B’A Fanout Connection