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Doc.: IEEE 802.11-00/383 Submission November 2000 Yasuo Harada, Matushita Electric Slide 1 A consideration on FEC Bit error Performance of concatenation.

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Presentation on theme: "Doc.: IEEE 802.11-00/383 Submission November 2000 Yasuo Harada, Matushita Electric Slide 1 A consideration on FEC Bit error Performance of concatenation."— Presentation transcript:

1 doc.: IEEE /383 Submission November 2000 Yasuo Harada, Matushita Electric Slide 1 A consideration on FEC Bit error Performance of concatenation of Viterbi decoder and RS code Yasuo Harada Matsushita Electric Industrial Co. Ltd.

2 doc.: IEEE /383 Submission November 2000 Yasuo Harada, Matushita Electric Slide 2 Concatenated Error Correction Scheme Concatenation FEC scheme used in Digital Broadcasting system such as in Satellite, Cable, terrestrial system for MPEG2 data Robust error correction feature is obtained by concatenation of Viterbi and RS code Viterbi decoder in a phy specification and FEC option provide this improvement in e

3 doc.: IEEE /383 Submission November 2000 Yasuo Harada, Matushita Electric Slide 3 Features of Viterbi decoder Viterbi decoder with a high error correction capability Viterbi decoder produces burst bit error when errors occur over its correction capability Interleave is very effective with concatenation of RS code and Viterbi decoder

4 doc.: IEEE /383 Submission November 2000 Yasuo Harada, Matushita Electric Slide 4 Example of Bit error performance simulation condition.AWGN No PhaseNoise 16QAM R=3/4 Packet Size 1 Word = 255 Byte (RS(255,239)) 1 Payload = 4 Word (1020 Byte) Interleave MATRIX 255Byte×4


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