Presentation on theme: "Doc.: IEEE 802.15-09-0046-00-003c Submission Slide 1 January, 2009 Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission."— Presentation transcript:
doc.: IEEE c Submission Slide 1 January, 2009 Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [Comment resolution #118 (E)] Date Submitted: [Jan ] Source: [Sandrine Roblot] Company: [France Telecom Orange] Address: [4 rue du clos courtel Cesson-Sévigné FRANCE] Voice: , FAX: , Re:  Abstract: [Comment resolution for CID118 on LB49] Purpose: [To be considered in IEEE c standard] Notice: This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P
doc.: IEEE c Submission Slide 2 January, 2009 Bit interleaver description – Figure 156 Comment Suggested Remedy Comment 118What means of doted line to express the block of bit inter leaver. Please explain why doted line is needed otherwise remove it.
doc.: IEEE c Submission Slide 3 January, 2009 Bit interleaver description – Figure 156 Explanation: This figure presents the turbo-based interleaver structure. The interleaver rule is based on an iterative structure, as illustrated in Figure 156, in order to increase the scalability of the interleaver. Figure 156 does not present all the iterations (blocks labeled I) that could be performed by such a process but only a few of them. That's why doted lines are used : to show that, depending on the interleaving parameters, there can be other iterations (blocks). Note that these doted lines are used in that figure (Fig. 156 in D04) in the same context than in previous versions of the bit interleaver description (Fig. 158 in D02).