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**Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard**

Kiran Gunnam1, Gwan Choi2, Weihuang Wang2, Mark Yeary3 1Marvell Semiconductor, 2Texas A&M University, 3University of Oklahoma

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**Regulatory Patent Information**

The material contained in this presentation and ISCAS paper has features which are contained in the patent disclosure for LDPC decoding architectures. Written permission from Texas A&M University System is needed for the use of the concepts presented here.

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**Outline Introduction of LDPC Problem Statement**

On-the-fly computation for QC-LDPC Multi-rate Layered Decoder Results and performance comparison

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Example LDPC Code

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**Decoder Architectures**

Fully Parallel Architecture: All the check updates in one clock cycle and all the bit updates in one more clock cycle. Huge Hardware resources and routing congestion. Serial Architecture All Check updates and bit updates in a serial fashion. Huge Memory requirement. Memory in critical path.

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**Semi-Parallel Architecture**

Check updates and bit updates using several units. Partitioned memory by imposing structure on H matrix. Practical solution for most of the applications. Complexity differs based on architecture and scheduling

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Problem Statement The authors in [1] reported that 95% of power consumption of the decoder chip developed results from memory accesses. The authors in [2] reported that 50% of their decoder power is from memory accesses. Memory access is a bottleneck in preventing full utilization of units. Efficient implementations for the irregular codes is a hard problem [1] Yijun Li et al, "Power efficient architecture for (3,6)-regular low-density parity-check code decoder,“ IEEE ISCAS 2004 [2] Mansour et al “A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip”-IEEE Journal of Solid-State Circuits, March 2006

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**Irregular QC-LDPC codes**

Different base matrices to support different rates. Different expansion factors (z) to support multiple lengths. All the shift coefficients for different codes for a given rate are obtained from the same base matrix using modulo arithmetic

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Irregular LDPC codes

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Irregular LDPC codes

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Irregular LDPC codes

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Irregular LDPC codes Existing implementations [3] show that these are more complex to implement. However these codes have the better BER performance and selected for IEEE e and IEEE n. It is anticipated that these codes will be the default choice for most of the standards. We show that with out-of-order processing and scheduling of layered processing, it is possible to design very efficient architectures [3] Hocevar, D.E., "A reduced complexity decoder architecture via layered decoding of LDPC codes," IEEE Workshop on Signal Processing Systems, SIPS pp , Oct. 2004

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**On-the-fly computation**

This research introduces the following concepts to LDPC decoder implementation [ICASSP’04,Asilomar’06,VLSI’07,ISWPC’07,ISCAS’07,ICC’07] Block serial scheduling Value-reuse, Scheduling of layered processing, Out-of-order block processing, Master-slave router, Dynamic state, Speculative Computation Run-time Application Compiler [support for different LDPC codes with in a class of codes. Class:802.11n,802.16e,Array, etc. Off-line re-configurable for several regular and irregular LDPC codes] All these concepts are termed as On-the-fly computation as the core of these concepts are based on minimizing memory and re-computations by employing just in-time scheduling.

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**New Dataflow Graph for Layered Decoding**

Decoder architecture

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**Decoder for Irregular codes**

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**Pipeline for Irregular codes**

R selection for Rnew operates out-of-order to feed the data for PS processing of next layer

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**Out-of-order layer processing for R Selection**

PS processing R selection R selection is out-of-order so that it can feed the data required for the PS processing of the second layer. So here we decoupled the execution of R new messages with the execution of CNU processing. Here we execute the instruction/computation at precise moment when the result is needed!!!

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**Out-of-order block processing for R Selection**

PS processing R selection Re-ordering of block processing . While processing the layer 2, the blocks which depend on layer 1 will be processed last to allow for the pipeline latency. In the above example, the pipeline latency can be 5. The vector pipeline depth is 5.so no stall cycles are needed while processing the layer 2 due to the pipelining. [In other implementations, the stall cycles are introduced – which will effectively reduce the throughput by a huge margin.] The minimum number of stall cycles due to the memory configuration is 1.(due to FS write) It is possible to change the memory configurations such that FS write and FS read cycles are stall cycles. In this case, the FS memory will be a single port memory. Now there will be 2 stall cycles.

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Cyclic Shifter This arrangement can support the base matrices having the expansion factors multiples of z by using z x z cyclic shifters. Works for n in which the expansion factors are 27,54,81

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Results

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**Layered Decoder Throughput Results-FPGA, 802.11n**

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**Layered Decoder Throughput Results-ASIC, 802.11n**

Proposed decoder takes around 100K logic gates and memory bits. [4] takes 375 K logic gates and RAM bits for memory for a throughput of 940 Mbps [5] takes 195 K logic gates for pipelined implementation, plus 77, 760 bits memories. for a throughput of 1 Gbps [4] Rovini, M.; L'Insalata, N.E.; Rossi, F.; Fanucci, L., "VLSI design of a high-throughput multi-rate decoder for structured LDPC codes," Digital System Design, Proceedings. 8th Euromicro Conference on , vol., no.pp , 30 Aug.-3 Sept. 2005 [5] Y.Sun, M. Karkooti and J. R. Cavallaro, “High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems” Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software. Oct 2006, Dallas.

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**Our other LDPC Publications**

K.Gunnam, G. Choi, M.B. Yeary, and M. Atiquzzaman, “VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax,” Accepted for IEEE International Conference on Communications (ICC), June 2007 K. Gunnam,W. Wang, G. Choi and M.B. Yeary, “VLSI Architectures for Turbo Decoding Message Passing Using Min-Sum for Rate-Compatible Array LDPC Codes,” IEEE International Symposium on Wireless Pervasive Computing (ISWPC), February 2007. K.Gunnam, G. Choi and M.B. Yeary “A Parallel Layered Decoder Architecture for Array LDPC Codes,” IEEE VLSI Design Conference (VLSI), January 2007 K.Gunnam, G. Choi, W. Wang, E. Kim, and M.B. Yeary, “Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation”, 40th Asilomar Conference on Signals, Systems and Computers (Asilomar), October 2006 K.Gunnam, G. Choi and M. B. Yeary, “An LDPC Decoding Schedule for Memory Access Reduction”, IEEE International Conference on Acoustics, Speech, and Signal Processing, May 2004 (ICASSP)

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Other Publications 5. K. Gunnam, G. Choi, and M. Yeary, “A low-power preamble detection methodology for packet based RF modems on all-digital sensor front-ends,” IEEE-IMTC, Warsaw, May 2007. 4. K.Gunnam, K.Chadha and M.B.Yeary, “New Optimizations for Carrier Synchronization in Single Carrier Systems,” IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2005). 3. J. Valasek, K.Gunnam, J. Kimmett, D. Hughes and J. Junkins., "Vision Based Sensor and Navigation System for Autonomous Aerial Refueling," Journal of Guidance and Control, October 2005. 2. K.Gunnam, D.C.Hughes, J.L.Junkins and N.Kehtarnavaz,."A Vision Based DSP Embedded Optical Navigation Sensor” IEEE Sensors Journal, vol.2.pp ,Oct 2002. 1. K.Gunnam, D.C.Hughes, J.L.Junkins and N.Kehtarnavaz,."A DSP Embedded Optical Navigation System" Proceedings of Sixth IEEE International Conference on Signal Processing, ICSP 2002.

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Acknowledgements NASA, ONR, DoD, Texas Instruments grants for the research Intel, Star Vision, Schlumberger for the research internships TAMU Ph.D. scholarship. Marvell who is supporting further development of this work in the commercial products

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Thank you !

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