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Presented By David Q. Kelly Principal Investigator: Sanjay K. Banerjee Microelectronics Research Center University of Texas at Austin Austin, Texas, U.S.A. Germanium-Carbon Layers on Si for Enhanced-Channel-Mobility MOSFETs

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Advantages of Germanium Bulk Ge has higher electron (2.5×) and hole (4×) mobility than Si –Buried channel PMOS has shown very high mobility enhancements Compatible with high-κ gate dielectrics Lower temperature processing GeSi n (cm 2 /V·s) 39001500 p (cm 2 /V·s) 1900450 E g (eV) 0.661.12

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Background: Disadvantages of Germanium Native GeO 2 cannot be used as gate dielectric –Thermally desorbs above 420°C –Soluble in water Requires surface passivation for good interface with high-κ dielectrics Smaller energy bandgap –Increased subthreshold leakage current Poor NMOSFET Performance –Would require a separate approach

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Graded Si 1-x Ge x Buffer Layers (MIT) Thick, relaxed, graded SiGe virtual substrates with compressively-strained Ge top layer Calls for a CMP step to remove surface roughness on the virtual substrate prior to strained Ge layer growth Currie, et al. APL 1998

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Other Approaches to Ge on Si Cyclical Thermal Annealing –L. Kimerling (MIT) –Two-step growth following by cyclical annealing at 900°C and 780°C Surfactant-mediated epitaxy –K. R. Hofmann (Germany) –Surfactant doping (Sb atoms) –Has only been demonstrated using MBE Thermal annealing in hydrogen –Saraswat (Stanford) –Pure Ge layer grown on Si is annealed in hydrogen to fully relax layer –Low-defect density Ge layer is re- grown over relaxed layer Condensation of epitaxial SiGe –S. Takagi (Japan) / IBM –Could be promising for Ge-on- insulator –Requires SGOI substrate Cyclical Annealing Hydrogen Annealing Ge Condensation

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CVD Ge 1-x C x Grown Directly on Si Group at Arizona State University was the first to demonstrate Ge 1-x C x films grown directly on Si (100) by UHVCVD –Appl. Phys. Lett. 68 (17) pp. 2407-2409, 1996. –Chem. Mat. 8 (10) pp. 2491-2498, 1996. Key to achieving efficient C incorporation is to use precursors with pre-formed Ge–C bonds –Methylgermane CH 3 GeH 3 –Digermylmethane CH 2 (GeH 3 ) 2 –Trigermylmethane CH(GeH 3 ) 3 MOS devices never reported until now

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Ge 1-x C x Layer Growth by UHVCVD 4 n-type wafers cleaned using HF-last process Base pressure prior to deposition was 7.0×10 -10 Torr Growth Temperature 450°C Mixture of GeH 4 and CH 3 GeH 3 precursors introduced at deposition pressure of 5 mTorr Final layer thickness ~ 30 nm

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XTEM Results (30 nm Ge 1-x C x on Si) Larger area scan shows that Ge 1-x C x layer is epitaxial and has no visible threading dislocations –Strain relaxation is thought to occur through misfit dislocations confined at interface

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Ge 1-y C y Surface Roughness Dependence on Growth Temperature and C Incorporation Film quality depends on both the growth temperature and the amount of methylgermane flow –AFM RMS surface roughness improves with decreasing growth temperature –Higher carbon incorporation also leads to smoother film

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Very Low RMS Surface Roughness Measured by AFM Low growth temperature is important for achieving smooth Ge 1-x C x film Nearly atomically flat RMS Roughness = 0.32 nm Large 3D islands RMS Roughness = 31 nm 600°C Growth Temperature450°C Growth Temperature

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Ge 1-x C x 20 nm Si (001) Substrate glue (sample preparation) 20 nm Pure Ge Si (001) Substrate glue (sample preparation) XTEM Comparison of Ge 1-x C x on Si with pure Ge on Si Pure Ge grown at low temperature directly on Si shows large number of threading dislocations Not present in Ge 1-x C x layer Ge 1-x C x Pure Ge

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Threading dislocation densities cannot be calculated using conventional etch-pit techniques because Ge 1-x C x is too thin –Use a diluted etch pit solution in conjunction with atomic force microscopy (AFM) –30µm×30µm measurement window –Estimated density for Ge 1-x C x ~3×10 5 cm -2 Bulk GeGe 1-x C x on SiPure Ge on Si No etch pits 3 etch pits Numerous etch pits EPD technique was developed by UT-Austin Masters student Isaac Wiedmann 2.1×10 8 cm -2

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Si (001) Substrate Ge 1-x C x in-plane mismatch perpendicular mismatch Lattice Parameter and Strain Relaxation (XRD) a Ge 5.658 Å a || 5.598 Å a 5.679 Å a r 5.643 Å Ge 1-x C x Reciprocal space map of (224) reflection 78% relaxed

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Carbon Segregation Effects SIMS EFTEM Brighter regions correspond to higher C concentration Suggests chemical reaction of C with Si at the GeC/Si interface SIMS measured using standard prepared by ion implantation Higher C level at interface

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EELS Data Energy of the C plasmon peak energy increases as we get closer to the Ge 1 x C x /Si substrate interface This is evidence for the higher sp 3 character of the C atoms located near this interface This higher sp 3 character could indicate the presence C-containing interstitial complexes or substitutional C in Ge near the interface. Both of these are mechanisms for strain relaxation, which helps to explain the low density of threading dislocations in the films

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Thermal Stability: AFM and XRD Rocking Curves Layers were 30nm Ge 1-x C x with 5nm Si cap Ge 1-x C x peak in XRD rocking curve is shifting toward the Si peak –Lattice constant decreasing due to relaxation and Si diffusion RMS roughness measured by AFM increases slightly but remains smooth

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Effect of Annealing on Lattice Parameter (Si Diffusion, Relaxation) d 400 ratio defined as ratio of Si and Ge 1-x C x d-spacings measured using rocking curves with (004) reflection Shows that lattice parameter decreases below the value for fully-relaxed Ge –Most likely due to diffusion of Si atoms during annealing –Also due to strain relaxation Need to use reciprocal space maps for more precise lattice parameter measurement

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StepProcessNotes 1 Si Substrate Cleaning 2:1 H 2 SO 4 :H 2 O 2 piranha followed by 40:1 DI:HF 2Ge 1-x C x Growth 5 mTorr, GeH 4 and CH 3 GeH 3, 450C 3 Surface pretreatment Si control - 40:1 DI:HF BC Ge 1-x C x - 40:1 DI:HF SC Ge 1-x C x - None 4PVD HfO 2 /TaN ~7nm HfO 2, 200nm TaN 5Gate Pattern Lithography (Ring-type gates), RIE w/ CF 4 6Ion Implant BF 2, 5×10 15 cm -2, 25 keV 7Contact LTO 530C, 2 hrs., 200nm 8Contact/Metal Lithography, sputtered Al 9Forming gas 6 slm, 450C, 30 min. R2R2 R1R1 R 1 = 75 µm R 2 = 85 µm L eq ~ 10 µm W eq ~ 500 µm PMOSFET Fabrication Process

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PMOSFET Device Structures (Buried- and Surface-Channel Devices) Ge 1-x C x BC Gate Stack n-type Si (001) Substrate Ge 1-x C x (30 nm) HfO 2 TaN Si cap layer (6 nm) Ge 1-x C x SC Gate Stack n-type Si (001) Substrate Ge 1-x C x (30 nm) HfO 2 TaN

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Ge 1-x C x HfO 2 /TaN MOS Capacitor C-V Characteristics No Si cap layer EOT 2.3 nm Leakage J @ 1V 3.3×10 -5 A/cm 2 D it 4.8×10 11 eV -1 cm -2 High V FB could be due to fixed negative charged introduced by diffusion of C atoms

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Ge 1-x C x HfO 2 /TaN MOS Capacitor C-V Hysteresis Measured using forward and reverse voltage sweeps 78 mV at 1 MHz 85 mV at 500 kHz About 250 mV dispersion between two measurement frequencies

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Ge 1-x C x BC and SC pMOSFETs Gate Leakage Current Higher gate leakage for surface-channel device Could be due to inadequate surface passivation prior to HfO 2 deposition and/or HfO 2 /Ge 1-x C x interdiffusion

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Output Characteristics for Buried-Channel Ge 1-x C x pMOSFET Good saturation behavior I Dsat = 10.8 µA/µm @ V GS -V T = 1.0 V 2× enhancement over Si control EOT = 1.9 nm W ~ 500 µm L ~ 10 µm

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Gate C-V Characteristic for BC pMOSFET Gate C-V shows buried-channel behavior Kink is due to valence band offset between Ge 1-x C x and Si cap layer Gate leakage (inset) is 2.6×10 -6 A/cm 2 @ -1V

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Linear I D and G m Characteristics for Buried-Channel Ge 1-x C x pMOSFET Si Control BC GeC 1.8 × enhancement in both I Dlin and G m over Si control I on /I off = 5×10 4

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Output Characteristics for Surface-Channel Ge 1-x C x pMOSFET I Dsat = 15.2 µA/µm @ V GS -V T = 1.0 V 3× enhancement over Si control EOT = 1.9 nm W ~ 500 µm L ~ 10 µm

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Linear I D and G m Characteristics for Surface-Channel Ge 1-x C x pMOSFET Si Control SC GeC 2× enhancement in both I Dlin and G m over Si control I on /I off < 10 2

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Subthreshold Characteristics for BC and SC Ge 1-x C x pMOSFETs Si Control GeC High subthreshold leakage makes SS calculation difficult I on /I off BC = >5×10 4, SC = >10 2 BC SC

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Effective Hole Mobility Comparisons BC and SC pMOSFETs exhibit 1.5× and 2.5× enhancement over universal Si, respectively

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