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Electrical Characterization and Reliability Group Evaluation of Charge Trapping Measurements and Their Application to High- Gate Stack Evaluation IEEE.

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Presentation on theme: "Electrical Characterization and Reliability Group Evaluation of Charge Trapping Measurements and Their Application to High- Gate Stack Evaluation IEEE."— Presentation transcript:

1 Electrical Characterization and Reliability Group Evaluation of Charge Trapping Measurements and Their Application to High- Gate Stack Evaluation IEEE Electron Device Society Meeting Chadwin D. Young SEMATECH, the SEMATECH logo, International SEMATECH, and the International SEMATECH logo are registered servicemarks of SEMATECH, Inc. AMRC, Advanced Materials Research Center, ATDF, the ATDF logo, Advanced Technology Development Facility, ISMI and International SEMATECH Manufacturing Initiative are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Introduction/Motivation Hf-based films are currently being studied to replace SiO 2 gate dielectrics in future technology nodes A major issue with high- transistors is trapped charge The high- film quality and its impact on device performance (i.e., I d -V g and mobility) is being investigated – Bulk traps, trapped charge (Kerber, Zhu, and Young) – Phonon scattering (M. Fischetti, E. Cartier, et al) – Crystallization of the high-, inducing charges (Yamaguchi, Bersuker) – Impact of metal gate (Intels IEEE Electron Device Letter) Measurements methodologies are needed to qualitatively and quantitatively determine trapped charge in high- gate stacks

3 Introduction/Motivation V t instability and device performance degradation have been extensively studied in high- gate stack structures – Fast transient charge trapping of substrate injected electrons is a major contributor to the instability and degradation Charge trapping during conventional DC measurements prevents evaluation of the intrinsic properties of high- dielectrics Previously reported pulsed I-V results may still be subject to fast transient charging (previous minimum charging time: 5 s at SEMATECH)

4 Introduction/Motivation Need to ensure proper evaluation of the threshold voltage shift ( V t ) Need to understand the effect of charge trapping on the extraction of intrinsic mobility Need to understand the impact of fast transient charging on the reliability assessment of high-

5 Objective To evaluate several charge trapping measurement methodologies – Capacitance-Voltage hysteresis – Stress and Sense (CVS w/ C-V around V fb ) – Fixed and Variable Amplitude Charge Pumping – Fast Transient (Single Pulse) Measurements were done on various hafnium-based gate stacks – MOCVD and ALD type dielectrics – Varying physical thickness – Polysilicon electrode and metal gate Show and discuss the results of these measurements

6 C-V Hysteresis Voltage sweep methodology shows that as the sweep widens, so does the hysteresis Notice the –1 V discharge condition (up traces identical) Self-consistent methodology must be used to avoid examples shown – electric field strength should be fixed

7 C-V Hysteresis Comparison-Metal v. Poly There is a reduction in V with a metal gate Notice that the inversion regime shows a larger hysteresis in each case

8 CVS with Interspersed CV There is a time delay between stress and C-V allowing relaxation of some of the trapped charge In addition, CV is taken around V fb which de-traps some substrate injected electrons

9 Substrate Injection for ALD HfO 2 Interspersed C-V measurements – Positive flatband shift indicating a net negative trapped charge – Notice the hysteresis widen as the stresses continue signifying electron trapping Plot of N t vs. injected charge, Q inj Noise here suggests an unstable extraction of V fb based on CV up- traces being so close together Inset: Pre-stress C-V data

10 Substrate Injection for MOCVD HfSi x O y Interspersed C-V measurements – Positive flatband shift indicating a net negative trapped charge – Notice the hysteresis widen as the stresses continue signifying electron trapping Notice larger V fb shifts than the previous example – Trapped charge is retained longer than ALCVD Larger quantity of trapped charge

11 Charge Pumping Measurements Charge pumping measurement: -Fixed Amplitude (FA) interface traps, N it, V base is stepped -Variable Amplitude (VA) bulk traps, N t, V top is stepped - rise and fall times t r and t f = 100 ns - traps fill from S/D during t r, empty into substrate during t f Charge pumping current is given by f= freq, A= channel area, N it = interface trap density

12 Charge Pumping (CP) on Various Gate Stacks FA CP and VA CP are done to assess trapping in the hybrid stack FA CP shows relatively low N it values for all hybrid stacks VA CP shows the 30/15 hybrid with the highest trapping density at V top < 1V Thinner hybrid stacks suggest lower trapping densities – However, scaled stacks takes off at 1.5V and beyond (see next slide) – Interpretation of the data is not straightforward…

13 Variable Amplitude CP Current and Gate Leakage Current Gate leakage is present in accumulation from gate to substrate In inversion, leakage component flows from source/drain to gate – Indirectly measured by enhancement in I cp due to enhanced carrier supply (enhanced injection) – S/D leakage current goes in the opposite direction of measured I cp, therefore not directly measured I cp I(d,g)I(s,g) INV I cp I(d,g)I(s,g) ACC IgIg

14 Charge Pumping for Process Characterization 3.5 nm HfSiO (20%) – 700C/800C N 2 O PDA Reduced N t values and flatter N t –V peak curves suggest that the higher temperature N 2 O PDA increases the interfacial layer thereby increasing the tunneling distance to traps in this silicate gate stack. Fixed Base, Variable Amplitude Charge Pumping (into inversion)

15 RLRL V DD VDVD VgVg Pulsed Transient Charge Trapping Measurement Setup Single Pulse Input: Width: 5 s< t PW < 100 s Rise, Fall times: t R =t F = s R L typically ~ 300 ohms V DD typically 100 mV Output V D pulse is digitized as 5000 readings versus time I D -V G and I D - time plots formed from I D (0.1V) = 0.1 * (V DD /V D – 1)/R L Device W/L and series resistance normalization applied as needed

16 Transient Charging in High- Gate Stacks Single Pulse I d -V g characteristics for different inversion biases illustrating increased trapping (V t shift) with increased inversion bias from substrate injected electrons for nMOS and negligible trapping for pMOS at these bias conditions The included nMOS DC ramp I d -V g result demonstrates the effect of charge trapping during the slower measurement

17 Plausible Charging Model The inversion channel electrons are lost due to tunneling through the interfacial layer and into the high- trap sites Thinner interface layers result in faster trapping Substrate injected electrons result in the decreased drive current and mobility seen in conventional DC measurement techniques

18 Single Pulse Output Data and Analysis Ih this case, the V t is measured at 50% of the max I d on 10 m x 1 m nFETs – The Vt is a composite effect of trapping and de-trapping Charge trapping increases with increasing inversion bias Note that the vertical drop at V g = 2.5V on the I d -V g curve is associated with the droop at the top of the I d – time current pulse. max I d

19 Measurement Comparison CVS with interspersed CV, variable amplitude charge pumping, and fast transient single pulse MOCVD Hafnium silicate of varying physical thickness, all with poly electrode – 2.5, 3.5, 4.0, 4.5 nm

20 Variable Amplitude Charge Pumping Variable amplitude CP was set up to mimic the single pulse as close as possible The trapped charge value is take on the final pulse (i.e., -1 to 2 V) Remember: Charge pumping measures a recombination current 2.5 kHz 100 s

21 Single Pulse Measurements Single pulse measurement – 10x1 Transistors – t r, t f, PW = 100 s – Pulse base = -1 V Hysteresis reduces as the nominal physical thickness reduces Time settings used may still have some transient chargeing in the results

22 Comparison Results Due to relaxation and measuring around V fb for the CVS with CV technique, trapped charge is lost Single pulse values for V t show that ~100 mV shift equates to ~1E11/cm 2 trapped charge Variable amplitude CP is on the same order of magnitude but 4x-5x less than single pulse All samples have O 3 interfacial layer For comparison, trapped charge is assumed to be at the silicon substrate interface

23 Ultra-short Pulse I-V Characterization of the Intrinsic Behavior of High- Devices

24 Approach System: Hafnium-based gate dielectric stacks with polysilicon gates Method: Ultra-short pulse I-V technique in the nanosecond range Goal: Illustrate negligible charge trapping with improved measurement performance through the use of an ultra-short pulse-based I-V technique – The findings presented herein suggest that the nanosecond capability provide close-to-intrinsic properties of high- gate stack structures over the previous mentioned time settings

25 Effect of Interfacial Layer on Charging In order to achieve EOTs below ~0.8 nm, scaling of the interfacial layer (IL) may be required This reduces the tunneling distance to the high- bulk traps Trapping may occur on the rise time of the pulse which has typically been assumed to be void of trapping HF Last Interface Treatment Physically ~ nm thick IL Nitrogen baring IL High- : 5 nm ALD HfO 2

26 Nanosecond Pulse Set Up In order to ensure close-to-intrinsic properties of high- stacks, an ultra-short pulse I-V capability with faster acquisition times is required

27 Applications Single Pulse I d – V g I d – Time Ramped Pulse I-V I d – V g I d – V d = Data points are averaged here for ramped pulse I-V

28 Benchmark/Calibration of a 35 ns Pulse Width Benchmark and calibration were carried out on a SiO 2 control oxide – Pulse width = 35 ns, rise and fall times = 2 ns – Ground-Signal-Ground (G-S-G) probes, connections, and devices were used Ramped Pulse I d -V g Ramped Pulse I d -V d

29 Drive Current Degradation Pulsed I d versus time characteristics illustrating the degradation in drive current over time due to channel electron trapping into the high- – a) Pulse width = 50 ns – b) Pulse width = 100 s, 50 s, and 10 s – Charge trapping degradation of I d can be seen

30 Expanded Ultra-Short Pulse Result Pulsed I d versus time characteristics illustrating no observable degradation in drive current over time due to the lack of channel electron trapping in the high- No I d degradation seen in the thin interfacial layer sample (right)

31 Comparison of Old to New Single pulse charge trapping measurement on HfSi x O y NMOS transistors: – Rise and fall time of the pulse is 25 ns and the pulse width is 50 ns with no hysteresis in two I d -V g curves using the ultra-short pulse set up – Rise and fall time of the pulse is 5 s and the pulse width is 5 s with hysteresis and noise in the I d -V g curves using the set up previously reported Old New

32 Application of Ultra-short Ramped Pulse 35 ns pulse width saturation current of this high- sample has increased by as much as 40% at high V g over conventional DC

33 Summary I C-V hysteresis is good for qualitative understanding of trapping that is occurring Stress and sense loses trapped charge in the V fb measurement – Stress and sense with I d -V g to monitor threshold voltage shift is somewhat better Variable amplitude charge pumping could be an excellent process monitoring tool for measuring the trapped charge When properly done, Pulse I-V is an excellent benchmark in measuring and quantifying trapped charge in high- gate stacks

34 Summary II Thin interfacial layers result in faster trapping, thereby reducing the time for the onset of transient charging A unique nanosecond regime pulse I-V measurement allows close-to-intrinsic characterization of high- gate stacks due to no observable trapped charge in pulsed I-V characterization Ultra-short pulse I-V demonstrates significant improvement in high- device performance when compared to DC methods

35 Comparison of Trap-Free Mobility Extraction Techniques for High- Gate Dielectrics

36 Outline Introduction/Motivation Approach Mobility Extraction Techniques – Split C-V – NCSU CVC and Mob2d – Kerber, et al, pulsed mobility extraction – Combine pulsed I d -V g with CVC and Mob2d Application/Evaluation of Mobility Extraction Methods Summary

37 Approach System: Hafnium-based gate stacks and control SiO 2 Method: Various mobility extraction algorithms: – Conventional split C-V ( benchmark) – NCSU CVC and Mob2d – Kerber, et al, pulsed mobility methodology – NEW Combine Pulsed I d -V g, CVC, and Mob2d Goal: To evaluate and compare intrinsic mobility extraction techniques in the presence of trapped charge

38 Split C-V Mobility Extraction Measurements – Separately measured inversion and depletion C-V characteristics at 100 kHz on W/L = 20/20 m – Integrate C-V curve (area under the curve) to obtain Q inv and Q b – Channel conductance from differential I d -V g measurements at 20 mV and 40 mV

39 Split CV and Mob2d Differences Split C-V N inv does not approach zero Since Q inv is in the denominator, mobility goes to zero (I d is small) Difference in Mob2d model I d to measured I d creates the up-turn in the low field regime

40 Kerber Mobility Extraction Technique directly measures N inv and uses pulse I d -V g data N inv is extracted by taking advantage of the geometric component in charge pumping measurements – Measure I cp using fast rise, fall times and long channel device (I cp includes N inv and N trap ) – Use proper CP methodology to extract N trap – Subtract N trap to leave only N inv Pulse I d -V g data collected Calculate the E eff and eff

41 NEW: Pulsed I d -V g with CVC and Mob2d CVC provides EOT (C ox ), substrate doping (N sub ), and poly doping (N poly ) to Mob2d for the mobility extraction – C-V hysteresis data should be evaluated by CVC to determine if there are any differences in extracted C ox, N sub, and N poly – N sub from CVC should be robust since C min is not significantly affected by trapped charge – C ox is extracted from the depletion and accumulation where trapped charge is minimal

42 Pulsed I d -V g with CVC and Mob2d (cont.) CVC on forward and backsweep C-V data shows no significant change in N sub, C ox, N poly A trap free I d -V g curve is done with the pulsed measurement With CVC of the transistor and pulsed I d -V g of a 10x1 m 2 transistor, Mob2d can be executed to provide a trap free mobility Accumulation InversionInversion Accumulation O 3 /3 nm ALD HfO 2 /Poly

43 CVC/Mob2d With Pulsed I d -V g on 2 nm SiO 2 Demonstration of CVC/Mob2d with Pulsed I d -V g on control SiO 2 sample yields excellent agreement with CVC/Mob2d with DC I d -V g

44 CVC/Mob2d Extraction and Kerber (cont.) Excellent agreement between CVC/Mob2d and Kerber High field mobility is quite close to the universal electron mobility for the particular samples shown

45 Summary CVC and Mob2d on 2 nm SiO 2 – Split C-V and Mob2d eff vs. E eff ~ same in the high field while split C-V is shifted and lower in the low field regime NEW - Pulsed I d -V g with CVC/Mob2d – Requires only two measurements (C-V and pulsed I d -V g ) – Simple, automated analysis/extraction verified on SiO 2 – Excellent agreement when benchmarked with Kerber for high- samples used

46 Threshold Voltage Instability: Electron Trapping Reversible and repeatable electron trapping Sim et al, SSDM 2004 Minimal trap generation: filling pre-existing traps Trapping processes: Fast initial – Slow long stress

47 References A. Kerber, et al, presented at INFOS, Barcelona, Spain, pp. WS1-5, June 2003 G. Groeseneken, et al., "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Transactions on Electron Devices, vol. ED-31, pp , C.D. Young, et al., Charge Trapping and Mobility Degradation in MOCVD Hf Silicate Gate Dielectric Stack Structures, presented at ESC Conference, Orlando,FL, Oct , Y. Zhao, C.D. Young, and G.A. Brown, Semiconductor International, Oct. 2003, pp. 51 S. Zafar, et. al., Applied Physics Letters, Vol 81, No. 14, p. 2608, 2002 S. Zafar, et. al., Journal of Applied Physics, Vol 93, p. 9298, 2002

48 References [1]G. Bersuker, P. Zeitzoff, J. Barnett, N. Moumen, B. Foran, C. D. Young, J. J. Peterson, and P. Lysaght, "Interface- Induced Mobility Degradation in High-k Transistors," Japanese Journal of Applied Physics, vol. 43, pp. 7899, [2]G. Bersuker, J. H. Sim, C. D. Young, R. Choi, P. Zeitzoff, G. A. Brown, B. H. Lee, and R. W. Murto, "Effects of Pre- existing Defects on Reliability Assessment of High-K Gate Dielectrics," Microelectronics Reliability, vol. 44, pp. 1509, [3]G. Bersuker, J. H. Sim, C. D. Young, R. Choi, B. H. Lee, P. Lysaght, G. A. Brown, P. Zeitzoff, M. Gardner, R. W. Murto, and H. R. Huff, "Effects of Structural Properties of Hf-Based Gate Stack on Transistor Performance," presented at 2004 Spring Meeting of the Material Research Society, [4]G. Bersuker, P. Zeitzoff, J. H. Sim, B. H. Lee, R. Choi, G. A. Brown, and C. D. Young, "Mobility Evaluation in High-K Devices," presented at IEEE Intl. Integrated Reliability Workshop Final Report, [5]R. Choi, S. Rhee, J. C. Lee, B. H. Lee, and G. Bersuker, "Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress," IEEE Electron Device Letters, vol. 26, pp. 197, [6]J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Transactions on Electron Devices, vol. 43, pp. 1981, [7]A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO 2 /HfO 2 dual layer gate dielectrics," IEEE Electron Device Letters, vol. 24, pp. 87, [8]A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Characterization of the V T instability in SiO 2 /HfO 2 gate dielectrics," presented at 41st Annual IEEE Intl. Reliability Physics Symp. Proc., [9]A. Kerber, E. Cartier, L. A. Ragnarsson, M. Rosmeulen, L. Pantisano, R. Degraeve, Y. Kim, and G. Groeseneken, "Direct measurement of the inversion charge in MOSFETs: application to mobility extraction in alternative gate dielectrics," presented at Symp. on VLSI Technology Digest of Tech. Papers, [10]J. C. Lee, H. J. Cho, C. S. Kang, S. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. Choi, and M. Abkar, "High-k dielectrics and MOSFET characteristics," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, [11]B. H. Lee, C. D. Young, R. Choi, J. H. Sim, G. Bersuker, C. Y. Kang, R. Harris, G. A. Brown, K. Matthews, S. C. Song, N. Moumen, J. Barnett, P. Lysaght, K. S. Choi, H. C. Wen, C. Huffman, H. Alshareef, P. Majhi, S. Gopalan, J. J. Peterson, P. Kirsh, H.-J. Li, J. Gutt, M. Gardner, H. R. Huff, P. Zeitzoff, R. W. Murto, L. Larson, and C. Ramiller, "Intrinsic Characteristics of High-k Devices and Implications of Fast Transient Charging Effects (FTCE)," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, [12]C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, and F. Martin, "Characterization and modeling of hysteresis phenomena in high K dielectrics," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, [13]C. G. Sodini, T. W. Ekstedt, and J. L. Moll, "Charge accumulation and mobility in thin dielectric MOS transistors," Solid State Electronics, vol. 25, pp. 833, 1982.

49 References [14]C. D. Young, A. Kerber, T. H. Hou, E. Cartier, G. A. Brown, G. Bersuker, Y. Kim, J. Gutt, P. Lysaght, J. Bennett, C. H. Lee, S. Gopalan, M. Gardner, P. M. Zeitzoff, G. Groeseneken, R. W. Murto, and H. R. Huff, "Charge Trapping and Mobility Degradation in MOCVD Hafnium Silicate Gate Dielectric Stack Structures," presented at 203rd Fall Meeting of the Electrochemical Society, Physics and Technology of High-K Gate Dielectrics - II, Orlando, FL, [15]C. D. Young, G. Bersuker, G. A. Brown, P. Lysaght, P. Zeitzoff, R. W. Murto, and H. R. Huff, "Charge trapping and device performance degradation in MOCVD hafnium-based gate dielectric stack structures," presented at 42nd Annual IEEE Intl. Reliability Physics Symp. Proc, [16]C. D. Young, P. Zeitzoff, G. Bersuker, and R. Choi, "Comparison of Trap-free Mobility Extraction Techniques for High- Gate Dielectrics," presented at International Workshop on Electrical Characterization and Reliability for High- Devices, [17]C. D. Young, Y. Zhao, M. Pendley, B. H. Lee, K. Matthews, J. H. Sim, R. Choi, G. A. Brown, R. W. Murto, and G. Bersuker, "Ultra-Short Pulse Current - Voltage Characterization of the Intrinsic Charactistics of High-k Devices," to be published in Japanese Journal of Applied Physics, vol. 44, [18]C. D. Young, R. Choi, J. H. Sim, B. H. Lee, P. Zeitzoff, Y. Zhao, K. Matthews, G. A. Brown, and G. Bersuker, "Interfacial Layer Dependence of HfSi x O y Gate Stacks on V t Instability and Charge Trapping Using Ultra-short Pulse I-V Characterization," presented at to be presented at the 43rd Annual IEEE Intl. Reliability Physics Symp. Proc, [19]P. M. Zeitzoff, C. D. Young, G. A. Brown, and K. Yudong, "Correcting effective mobility measurements for the presence of significant gate leakage current," IEEE Electron Device Letters, vol. 24, pp. 275, [20]Y. Zhao, C. D. Young, M. Pendley, K. Matthews, B. H. Lee, and G. A. Brown, "Effective Minimization of Charge Trapping in High-k Gate Dielectrics with an Ultra-Short Pulse Technique," presented at Intl. Conf. on Solid State and Integrated Circuit Technology, [21]W. Zhu, J.-P. Han, and T. P. Ma, "Mobility Measurements and Degradation Mechanisms of MOSFETs Made With Ultrathin High-k Dielectrics," IEEE Transactions on Electron Devices, vol. 51, pp. 98, [22]W. J. Zhu and T. P. Ma, "Temperature dependence of channel mobility in HfO 2 -gated NMOSFETs," IEEE Electron Device Letters, vol. 25, pp. 89, 2004.


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