Presentation on theme: "CTL Standard for Memories Standardizing the Test View of Memories."— Presentation transcript:
CTL Standard for Memories Standardizing the Test View of Memories
Meeting Agenda 9:30 Attendees Introduction All 9:45 Standardization objectives Saman 10:00 Discussion around the Objectives All 11:00 Memory Specific Test requirements Saman To lead the discussion 12:00 Lunch time..... 1:00 CTL Role Saman/Rohit 2:00 Coffee Break (Sponsored by LogicVision) 2:30 Logistics discussion All –Working group composition – Meetings/conf calls frequency –Group members responsibilities 3:30 Standardization order All 4:30 Adjourn
Standardization Objectives Test View of a Memory Needs to be More detailed than User View –Physical Information Number of Rows, Columns Memory Cell Orientations and layout Bit Grouping Bit Line Twisting …. –Redundancy Information –Repair Information –Multi-port Use –Access Modes –Addressing Modes –Use of ECC –Scan Test Specific Logic
Standardization Objectives EDA Industry Use Proprietary Modeling Schemes –Scan Test and BIST Memory User Need the Test/BIST Model Same Memory is used by Multiple Users Memory Providers Generate the Test Models based on Customer Requirements –Multiple Models for the Same Memory Validating the Models –Responsibility? All Models Convey the Same Information –More or Less
Standardization Objectives Unify All Models into one Common Model –Agreed on between all Parties EDA, Memory Providers and Users Use CTL as a Standardization Language –Some Constructs are Already There –Need to add More Independent of How to test the Memory –Memory Test Algorithm should not be the Focus
Memory Specific Test Requirements Several Aspects to be considered –Mostly Static Information Memory Level Information –Example: Address Segmentation Lower Level Information –Example: Ports and their Functions
Memory Level Information Memory Type –SRAM, DRAM, ROM, FLASH, Single Program ROM –Synchronous, Asynchronous Memory template Name Logical Ports –(x)RW, (y)R, (z)W, Retention Time Bypass Mode Minimum Hold Time Write Mode Operation (Select During Write Through) Data Out Stage –Flop, Latch, None Address Configuration –Logical Physical Address Map –Count Ranges for Bank, Row, Column –Physical Address Map Address Transition Delay Physical Data Map Physical Data Bits Grouping Write Enable Maping Tri State condition
Memory Level Information Redundancy Information –Redundant Rows, Columns, Row and Columnls –Address Fuse and Fuse Map Repair Information –Soft/Hard ECC Information –#of ECC bits –Accessibility of ECC Bits
Lower Level Information Ports Information –Port Name –Port Range [L:R] –Direction (Input, Output, InOut) –Logical Port relationship –Polarity (Active High/Low) – Port Function Data, Address, BistClock, ReadEnable, WriteEnable, Clock, GroupWriteEnable, Logic High, LogicLow, None, Open, OutputEnable, ScanTest, Select, | ShadowAddressEnable | ShiftEnable, Active, CAS, RAS, Refresh, ECCDisable, [User defined] –Status During Scan (Enable, Disable, Observe) –Scan Test Functions (ScanIn, ScanOut, ScanEnable)
Lower Level Information Memory Access Information –How to read, Write, and other Functions –Need specific waveforms –May have Multiple Access Modes Normal, Burst 2, Burst 4, … May be considered Application Specific –Do we need to standardize this?
Role of CTL CTL Mode internal Block –Defines Attributes for Input and outputs –Starting Point Does not cover all port types and fuctions –data_type –testcontrol_subtype –testdata_subtype –Need to go beyond the ports to cover Memory Level
Logistics Discussion Working group composition –Are we missing a segment from the Industry? –Need to elect a Chair, Vice Chair Meetings/conf calls frequency –Two Face to Face Meetings per year @VTS and @ ITC We will choose a scribe at the meeting Hopefully one year is enough –Conference calls once a month Decide on Day/Time/Length Minutes to be posted (Where/How?) Actions collected and tacked by the Chair –Use CTL Standard for Documentation Group members responsibilities –Share Your Knowledge –Get your Company Agreement –We need to know if your company holds patents on the Standard –Follow on with your commitment actions –Leave Politics out of it No need to know which tool is best Keep the chair informed of conflicts
Standardization Order Where do we start? –Ports and Their Functions Agree on them Add them to the CTL data_type –How do we do the handle the Memory Level Information?