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Mixed-Signal Test Bus IEEE1149.4 1 IEEE 1149.4 Mixed-Signal Test Bus An overview of this new testability bus standard, along with a discussion of the architecture.

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Presentation on theme: "Mixed-Signal Test Bus IEEE1149.4 1 IEEE 1149.4 Mixed-Signal Test Bus An overview of this new testability bus standard, along with a discussion of the architecture."— Presentation transcript:

1 Mixed-Signal Test Bus IEEE IEEE Mixed-Signal Test Bus An overview of this new testability bus standard, along with a discussion of the architecture and how to use it.

2 Mixed-Signal Test Bus IEEE IEEE : Mixed-signal Test Bus Standard n Development history n Basic guidelines n Test bus requirements n Standard architecture n Measurement example

3 Mixed-Signal Test Bus IEEE Development History n September 1991 sInformal meeting of 15 companies in San Jose, CA sDraft of mission statement, objectives, request to IEEE n October 1991 sITC meeting attracted 30 companies sWorking Group authorized by Test Bus Steering Committee n Working Group meetings sSince October 1991 sRegular meetings: 3 times per year at major test events

4 Mixed-Signal Test Bus IEEE Mission Statement To define, document, and promote the use of a standard mixed-signal test bus that can be used at the device, sub-assembly, and system levels to improve the controllability and observability of mixed-signal designs and to support mixed-signal built-in test structures in order to reduce test development time and costs, and improve test quality.

5 Mixed-Signal Test Bus IEEE Basic Guidelines n Providing test bus facilities to meet the mission objectives n Oriented toward industry: design, test, and manufacturing n Maintaining compatibility with test bus features n Coordinating with sIEEE and mainly the IEEE B-1994 sInternational industry and academic experts

6 Mixed-Signal Test Bus IEEE Basic Guidelines n IEEE does NOT seek to sSolve all mixed-signal test problems sDictate mixed-signal test strategies n IEEE DOES intend to sREDUCE the difficulty in mixed-signal testing sFACILITATE design-for-test sPROMOTE concurrent design & test approaches

7 Mixed-Signal Test Bus IEEE Mixed-Signal Printed Circuit Assembly

8 Mixed-Signal Test Bus IEEE Common Defects on a mixed-signal PCA n Shorts sD-D sA-A sD-A n Opens sZ sDirect Connections n Missing Component n Wrong Component DD D D D D A A D D D A A A D D D A A A D D D A DD D D D D A A D D D A

9 Mixed-Signal Test Bus IEEE CORE TDI TMS TCK TDO Virtual Test Probe CONNECTORPRINTED CIRCUIT ASSEMBLY IEEE Boundary-Scan Architecture

10 Mixed-Signal Test Bus IEEE Simple, Extended and Differential Interconnects

11 Mixed-Signal Test Bus IEEE Handling Analog Pins: Pre Digital section Test Access Port Analog inputs Digital inputs TDI TMS TCK Analog outputs Digital outputs TDO Analog section DBM DACADC TDI: Test Data In (1149.1) TMS: Test Mode Select (1149.1) TCK: Test ClocK (1149.1) TDO: Test Data Out (1149.1) DBM: Digital Boundary Module (Boundary-Scan Cell)

12 Mixed-Signal Test Bus IEEE Handling Analog Pins: with TDI: Test Data In (1149.1) TMS: Test Mode Select (1149.1) TCK: Test ClocK (1149.1) TDO: Test Data Out (1149.1) DBM: Digital Boundary Module (Boundary-Scan Cell) ABM: Analog Boundary Module Analog section Digital section Test Access Port Analog inputs Digital inputs TDI TMS TCK Analog outputs Digital outputs TDO DBM ABM DBM ABM

13 Mixed-Signal Test Bus IEEE Structure of a basic chip (minimal config) TMS TDI TDO TCK AT2 AT1 DIGITAL I/O PINS ANALOG I/O PINS TBIC (Test Bus Interface Circuit) Analog Test Access Port ATAP VHVH VLVL VGVG VHVH VLVL VGVG Internal Test Bus (AB1, AB2 ) Core Circuit Analog Boundary Module (ABM) Digital Boundary Module (DBM) Test Control Circuitry TAP Controller Instruction register and decoder Digital Test Access Port (TAP ) as in IEEE Digital Test Access Port (TAP) as in IEEE Boundar y Scan Path

14 Mixed-Signal Test Bus IEEE Analog Boundary Module: Input Pin Core TBIC V TH VHVH VLVL VGVG - + SB2SB1 AB1 AB2 Analog function pin AT1 AT2 SD Core disconnect Internal analog test bus ABM Switch Control From TDITo TDO SHSLSG oInput value can be sensed, digitised (against V TH ), and captured in the register oCurrent path into the core via AT1, AB1 and SB1 oAbility to disconnect the receiving core from the pin using SD and drive either a 1 or a 0 (SH or SL) oABMs can be implemented with actual switches or can be integral in the analog circuit.

15 Mixed-Signal Test Bus IEEE Analog Boundary Module: Output Pin n Dot 1 mode nLogic 1/0 to output via SH/SL nDigital signal input capture via comparison with V TH nCompatible with Extest, Preload/Sample n Analog mode: each pin can nsource an analog current via AB1/SB1, or n capture an analog voltage via SB2/AB2 nform a current return to V G (usually ground) via SG nbe disconnected from the core via SD Core TBIC V TH VHVH VLVL VGVG - + SB2 SB1 AB1 AB2 Analog function pin AT1 AT2 SD Core disconnect Internal analog test bus ABM Switch Control From TDITo TDO SHSLSG

16 Mixed-Signal Test Bus IEEE Analog Output Cell S9 S10 S5S8S7S6 V clamp AB1AB2 VHVH VLVL V TH S1 S4 S3 S2 AT1 AT2 Provision for interconnect test Bus connection and calibration n V H and V L allow fixed 1 and 0 values (for EXTEST) using S1, S2, S3, S4 n ATn disconnected from ABn via S5, S8 n Noise suppression via S9, S10, V clamp when ABn not in use

17 Mixed-Signal Test Bus IEEE Analog Boundary-Scan AT1 AT2 Z4 RZ1 Z3Z2 DR CORE TAP DR CORE TAP DR CORE TAP TDI TMS TCK TDO

18 Mixed-Signal Test Bus IEEE AT1 AT2 Z4 RZ1 Z3Z2 DR CORE TAP DR CORE TAP DR CORE TAP TDI TMS TCK TDO Constant Current Test of R, Measurement V1

19 Mixed-Signal Test Bus IEEE Test of R, Measurement V2 AT1 AT2 Z4 RZ1 Z3Z2 DR CORE TAP DR CORE TAP DR CORE TAP TDI TMS TCK TDO Constant Current

20 Mixed-Signal Test Bus IEEE Test of R, Result n R = (V2 - V1) / I n Results for three impedances (Z1, Z2, Z3) can be calculated and checked against correct values! n This metrology was proven and presented at the 1993 ITC by Ken Parker in a paper entitled: Structure and Metrology for an Analog Testability Bus by Ken Parker, John McDermid, and Stig Oresjo of HP.

21 Mixed-Signal Test Bus IEEE IEEE Types of Testing n Interconnect : Short, Open n Parametric Testing : Passive Element measurement n Internal Testing : DfT (Design for Test), BIST (Built-In Self-Test)

22 Mixed-Signal Test Bus IEEE For Further Information Officers: n Adam Osseiran, IEEE Working Group Chair Fluence Technology (Europe) n Stephen Sunter, Vice Chair LogicVision, CANADA n Adam Cron, Editor (previous Chair) Synopsys, USA n Elbert Nhan, Secretary Johns Hopkins University, USA n The IEEE Web page:

23 Mixed-Signal Test Bus IEEE To Learn more.... n The IEEE Standard Document SH94761-NCD; 59$ n ITC97, P8.2; IEEE D&TC, Fall 96, pp (Cron, Viewlogic) n ITC93, P15.2 (Parker et al, HP); ITC96, P15.1 (Whetsel, TI); ITC96, P4.2 (Lofstrom, KLIC) n K. Parker, Boundary-Scan Handbook: Analog & Digital, Kluwer, 1998 (2nd Edition). Chap. 7 n Perry, Fundamentals of Mixed-Signal Test, 1999, n A. Osseiran, Analog & Mixed-Signal Boundary Scan: a Guide to the Test Standard, Kluwer, 1999, n Next events : DATE00 (Paris), VTS00 (Montreal), ITC00 (Atlantic City)


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