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Design Methodology for Systems-on-Chip What is needed and what is not Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine.

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Presentation on theme: "Design Methodology for Systems-on-Chip What is needed and what is not Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine."— Presentation transcript:

1 Design Methodology for Systems-on-Chip What is needed and what is not Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine

2 Copyright 2002 Daniel D. Gajski 2 IEEE OCCS, 8/26/02 Who we are? Center for Embedded Computer Systems (www.cecs.uci.edu) Independent Research Organization in UC 15 faculty and over 60 Ph.D. students Methodology group: first system contract 1989 from SRC over 50 person years in system methodology since 1990 over 10 Ph.D. in system design flow since 1990 published first books on: –RTL Sythesis 1992 –Embedded Systems 1994 –System Design 2001 developed SpecC language leaders in SpecC Open Technology Consortium (www.specc.org) Inspired SystemC

3 Copyright 2002 Daniel D. Gajski 3 IEEE OCCS, 8/26/02 Outline System gap Semantics, styles and refinements RTL Semantics System-Level Semantics Where are we going? Conclusion

4 Copyright 2002 Daniel D. Gajski 4 IEEE OCCS, 8/26/02 Past Design Flow Simulate Capture & Simulate Physical Logic Specs Design Manufacturing Algorithms System Gap 1960s

5 Copyright 2002 Daniel D. Gajski 5 IEEE OCCS, 8/26/02 Past and Present Design Flow Describe Simulate System Gap Capture & Simulate Physical Logic Specs Design Manufacturing Algorithms 1960s Describe & Synthesize Manufacturing Specs Algorithms (software) Physical Logic Design 1980s

6 Copyright 2002 Daniel D. Gajski 6 IEEE OCCS, 8/26/02 Past, Present and Future Design Flow Communications Functionality Connectivity Protocols Timing Describe Simulate Physical Logic Specs Design Manufacturing Capture & Simulate Algorithms Describe & Synthesize Manufacturing Specs Algorithms (software) Physical Logic Design Specify, Explore & Refine Architecture Manufacturing Executable Spec Algorithms Physical Logic Design System Gap 1960s2000s1980s

7 Copyright 2002 Daniel D. Gajski 7 IEEE OCCS, 8/26/02 Missing Semantics: Simulation Dominated Design Flow Finite State Machine case X is when X1 => when X2 => Table Lookup ControllerMemory Simulatable but not synthesizable

8 Copyright 2002 Daniel D. Gajski 8 IEEE OCCS, 8/26/02 Y Chart BehaviorStructure Physical Synthesis Physical Design

9 Copyright 2002 Daniel D. Gajski 9 IEEE OCCS, 8/26/02 Y Chart BehaviorStructure Physical Logic Transistor RTL System

10 Copyright 2002 Daniel D. Gajski 10 IEEE OCCS, 8/26/02 Y Chart BehaviorStructure Physical Logic Transistor RTL System MoC

11 Copyright 2002 Daniel D. Gajski 11 IEEE OCCS, 8/26/02 Abstraction Algebra Algebra := SoC Algebra := Ordered set of transformations is a refinement iff model B = t m ( … ( t 2 ( t 1 ( model A ) ) ) … ) Question: { models } ? ; { transformations } ?

12 Copyright 2002 Daniel D. Gajski 12 IEEE OCCS, 8/26/02 Why Abstraction Algebra? 1. Enabling standard for ESDA 2. Discover truth behind system-level myths 3. Define system-level field (abstract semantics) 4. Introduce interoperability 5. Identify system-level methodology 6. Apply system-level methodology to SystemC, SpecC and others.

13 Copyright 2002 Daniel D. Gajski 13 IEEE OCCS, 8/26/02 Semantics, Styles & Refinements Each model uses well defined semantics Each model has simple style Each style uniquely expressed –no syntactic variance or semantic ambiguity Each model needs style checker Each model can be refined from its predecessor Clear refinement rules Clear application order of refinement rules Model refinements are verifiable

14 Copyright 2002 Daniel D. Gajski 14 IEEE OCCS, 8/26/02 RTL Computational Models Finite State Machine with Data (FSMD) Combined model for control and computation –FSMD = FSM + DFG Implementation: controller plus datapath FSMD model S1 S2 S3 Op2Op3 Op4 Op6 Op1 Op5 Op1Op2 Op3 Op1Op2

15 Copyright 2002 Daniel D. Gajski 15 IEEE OCCS, 8/26/02 RTL Processor

16 Copyright 2002 Daniel D. Gajski 16 IEEE OCCS, 8/26/02 RTL Synthesis Op2Op3 Op4 Op6 Op1 Op5 Op1Op2 Op3 Op1Op2 S1 S2 S3 FSMD model RTL Processor D QD Q D QD Q D QD Q Control inputs Next- state logic or Address generator Output logic or Program memory State register or PC Control outputs Control signals Bus 1 Bus 2 Selector Register Datapath outputs ALU Bus 3 Datapath Signal status Controller RegisterMemory RF SR IR Latch Data memory RTL

17 Copyright 2002 Daniel D. Gajski 17 IEEE OCCS, 8/26/02 RTL Synthesis Op1Op2 Op3 Op1Op2 S1 S2 S3 FSMD model Allocation Rescheduling Variable bindingOperation Binding Bus Binding FSM Synthesis Op2Op3 Op4 Op6 Op1 Op5 RTL

18 Copyright 2002 Daniel D. Gajski 18 IEEE OCCS, 8/26/02 System Computational Models Program State Machine –States described by procedures in a programming language Example: SpecC! (SystemC!) PSM model Proc

19 Copyright 2002 Daniel D. Gajski 19 IEEE OCCS, 8/26/02 System Synthesis PSM model Proc Memory µProcessor Interface Comp. IP Bus Interface Custom HW System architecture System

20 Copyright 2002 Daniel D. Gajski 20 IEEE OCCS, 8/26/02 System Semantics Objects: - Behaviors - Channels Composition: - Hierarchy - Order Sequential Parallel Piped States - Transitions TI TOC, TOS,... - Synchronization Objects: - Components Proc IP Memories IF - Connections Buses Wires Composition: (same as in Behavior Model) System

21 Copyright 2002 Daniel D. Gajski 21 IEEE OCCS, 8/26/02 System Synthesis PSM model Proc Memory µProcessor Interface Comp. IP Bus Interface Custom HW System architecture Profiling AllocationIF Synthesis Refinement Behavior BindingChannel Binding System Variable Binding

22 Copyright 2002 Daniel D. Gajski 22 IEEE OCCS, 8/26/02 System Synthesis (continued) RTL/IS Implementation + results MemRF State Control ALU Datapath PC ControlPipeline IF FSM IP Netlist RAM IR Memory State HCFSMD model FMDS4 FSMD5 FSMD3 FSMD2 FSMD1 RTL MoC

23 Copyright 2002 Daniel D. Gajski 23 IEEE OCCS, 8/26/02 EDA Approach: Simulation System RTL Logic Transistor VHDL, Verilog,

24 Copyright 2002 Daniel D. Gajski 24 IEEE OCCS, 8/26/02 C++ Approach: Syntax System RTL Logic Transistor

25 Copyright 2002 Daniel D. Gajski 25 IEEE OCCS, 8/26/02 MoC Approach: Diversity System RTL Logic Transistor MoC

26 Copyright 2002 Daniel D. Gajski 26 IEEE OCCS, 8/26/02 SystemC Approach: Language First Source: J. Kunkel, VP Synopsis, (CODES, May 2002) C++ SystemC C Supported Subset

27 Copyright 2002 Daniel D. Gajski 27 IEEE OCCS, 8/26/02 SpecC Approach: Semantics First System RTL Logic Transistor MoC

28 Copyright 2002 Daniel D. Gajski 28 IEEE OCCS, 8/26/02 SystemC/SpecC SpecC C++ SystemC C

29 Copyright 2002 Daniel D. Gajski 29 IEEE OCCS, 8/26/02 Quote from SystemC FUNCTIONAL SPECIFICATION FOR SYSTEMC 2.0 Version 2.0-M January 17, ACKNOWLEDGEMENTS Many companies and individuals have contributed time and resources in the development of both SystemC 1.0 and SystemC 2.0. Some of these contributors are listed in the contributors section of this specification and in the SystemC 1.0 Userss Guide. It should be noted that the fundamental mechanisms used to model communication and synchronization in SystemC interfaces, channels, and events - were inspired by similar constructs in Professor Daniel Gajskis SpecC language. (For further information, see SpecC: Specification Language and Methodology at

30 Copyright 2002 Daniel D. Gajski 30 IEEE OCCS, 8/26/02 Conclusion Work to be done: 1. Abstraction Levels 2. Model Semantics 3. Refinement Rules 4. Methodology 5. Language 6. Simulation, Synthesis, Verification Tools 7. ESDA Market/Community Emergence Prediction: No success in 7 without 1-6


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