1. AN OVERVIEW OF SIGMA-DELTA CONVERTERS
G. S. VISWESWARAN
PROFESSOR
ELECTRICAL ENGINEERING DEPARTMENT
INDIAN INSTITUTE OF TECHNOLOGY, DELHI
NEW DELHI
Telephone: (011) ; (011)

2. DOMAIN OF CONVERTERS
Sigma Delta
Successive Approx
Subranging/Pipelined
Flash
Signal bandwidth converted

3. PCM NYQUIST RATE A/D CONVERTERS
E[n] is a sample sequence of a random process uncorrelated with the sequence x[n].
The probability density of the error process is uniform over the range of quantization error i.e over /2
The error is a white noise process

4. PCM NYQUIST RATE A/D CONVERTERS
The variance of the noise power for a quantization level  is given by
This gives us an SNR

5. PCM NYQUIST RATE A/D CONVERTERS
In a Nyquist converter, the maximum signal to noise ratio that can be obtained for a sinusoidal input with a peak voltage of V is given by:
 Every additional bit  6dB of SNR.
eg. Digital audio with signal bandwidth = 20kHz.
If desired resolution = 18 bits
 SNR  110dB.

6. PCM NYQUIST RATE A/D CONVERTERS
What is the problem with getting 18 bits of resolution ?
1.      Nyquist rate converters essentially obtain output by comparing the input voltage to various reference levels. These reference levels are obtained by a process of reference division; using resistors or capacitors. Any mismatch in the resistors/capacitors results in loss of accuracy.
2.    For an ‘N’ bit converter, the required matching of elements is at least 1 part in 2N. Matching of components to > 10 bits (or > 0.1 %) is difficult.
3.   Nyquist rate converters require a sharp cutoff anti-aliasing filter.

7. OVERSAMPLED PCM CONVERTERS
Oversampled converters attempt to use relatively imprecise analog components with additional digital signal processing circuits to achieve high resolution. This is done using
  Oversampling - the sampling frequency is much higher than the signal frequency

8. OVERSAMPLED PCM CONVERTERS

9. OVERSAMPLED PCM CONVERTERS
Noise spectrum when sampled at fS >> 2fB
 Assume quantization noise is uniformly distributed, white and uncorrelated with the signal.
 Noise power folds back to –fS/2 to fS/2,  oversampled converters have lower noise power within the signal band.
 Out of band noise can be removed by a digital filter following the PCM converter.

10. OVERSAMPLED PCM CONVERTERS
We define Power Spectral Density of the output random Process is given by
For an oversampled PCM converter |Hx(f)| = |He(f)| = 1. White noise assumption states that Pe(f) = Se2(f)/fs which implies Pey(f) = Sey2(f)/fs. Thus the in band noise power is given by

11. OVERSAMPLED PCM CONVERTERS
We now see that the SNR ratio for this converter is
The spectrum of the (over) sampled signal can represented as follows:

12. OVERSAMPLED PCM CONVERTERS
 “16-bit resolution digital audio” Oversampled 8-bit converter to be used. To get an SNR = 110dB with fB = 20kHz, we need fS  2.64GHz.
This is still not good enough since the sampling frequency is too high. Further improvement can be obtained if noise shaping is used.

13. NOISE SHAPED OVERSAMPLED
PCM CONVERTERS
We see that for an A/D converter the output is given in general by Y(z) = X(z)Hx(z) + E(z)He(z)
We have seen OS PCM converter using | Hx(z)| = | He(z)| = 1. We can however realize another converter using | Hx(z)| = 1 but choose He(z) to shape the noise spectrum to improve the noise performance. Noise shaping or modulation further attenuates noise in the signal band to other frequencies. The modulator output can be low pass filtered to attenuate the out of band noise and finally down sampled to get Nyquist rate samples.

14. OVERSAMPLED NOISE SHAPING

15. NOISE SHAPED OVERSAMPLED
PCM CONVERTERS
 Noise is high pass filtered to get additional resolution
 Simplest z- domain high pass filter: 1 –z-1 We want an output Y(z) that contains the sun of the input and quantzation noise that is high pass filtered. i.e.
Y(z) = X(z) + (1-z-1)E(z) or
= z-1X(z) + (1- z-1)E(z)

16. NOISE SHAPED OVERSAMPLED
PCM CONVERTERS
Digital
Analog
One possibility is to first integrate the analog input, quantize it and then high pass filter it.

17. FIRST ORDER  MODULATION
The naïve system proposed has its own problems. The first problem is that since it is an open loop system, the integrator will saturate. It also requires matching between analog and digital portions of the circuit.
Y(z) = z-1X(z) + (1 – z-1) E(z)

18. FIRST ORDER  MODULATION

19. FIRST ORDER  MODULATION
 Linearized ‘z’ domain model gives
  Hx(z) = STF = z-1
He(z) = NTF = 1-z-1
 Assuming that the quantization noise is uncorrelated with the signal,
  Sxy(f) = Sx(f)Hx(f) 2
Sey(f) = Se(f)He(f) 2

20. FIRST ORDER  MODULATION
If fB<< fS
Thus we obtain the Noise Power as

21. Taking OSR to be of the form 2r we can obtain the SNR as

22. FIRST ORDER  MODULATION
Noise power coming out of First Order Modulator for an OSR of 128.

23. FIRST ORDER  MODULATION
Before we proceed to implement the transfer function we need to look in to certain realizatios in the sampled data domain. As the word  implies there is an integration involved. In the continuous domain, this requires resistance and capacitance.
As a designer we have the Capacity to Design but not the Resistance.

24. SWITCHED CAPACITOR CIRCUITS DOYEN OF SAMPLED DATA DESIGNS
Sampled Signals:
This gives a z transform

25. Realizing resistors for Sampled Data Circuits
The average value of current i1 or i2 is given by
This emulates a resistance of value R = T/C = 1/fC

26. OTHER REALIZATIONS OF R

27. SWITCHED CAP INTEGRATORS

28. SWITCHED CAP INTEGRATORS
During 1
During 2
Using z transforms, this reduces to

29. SWITCHED CAP INTEGRATORS
If  << 1/T, and using z = exp(jT) we get H(ejT) as
This circuit is then an integrator with a delay using the transformation s = (z-1)/T and is called the Forward Euler Integrator.

30. SWITCHED CAP INTEGRATORS
This is another integrator that gives a non inverting integration at the output and uses the transformation s = (1-z-1)/T and is called the Backward Euler Integrator.

31. SWITCHED CAP INTEGRATORS
The sampling capacitor Cs is now effectively Cs + CP, thus making the realized resistance R = T/(Cs + CP), different from the intended value --- needs correction, look for parasitic insensitive configuration.

32. SWITCHED CAP INTEGRATORS

33. SWITCHED CAP INTEGRATORS
At 1 Cs gets charged to Vin(nT) and
During 2
Giving us

34. SWITCHED CAP INTEGRATORS
This configuration gives

35. BACK TO SIGMA DELTA CONVERTERS
Implementation Imperfection in the first order sigma-delta modulator
§         Finite op-amp gain
§         Capacitance mismatch
§         Incomplete settling

36. FINITE OPAMP GAIN

37. FINITE OPAMP GAIN

38. FINITE OPAMP GAIN
Using charge conservations at the nth clock cycle, we have:
CSVI[n]- CSVd[n] = CF [Vo[n]+ Vd[n] – Vo[n-1] - Vd[n-1]]
Using Vo[n] = Avd[n] and writing in z domain

39. FINITE OPAMP GAIN
Output of the modulator is now given by
where NTF denotes the noise transfer function and STF denotes the signal transfer function,
 NTF ‘0’ is shifted away from DC. Neglecting the effect of the pole in the NTF,

40. FINITE OPAMP GAIN
= 1 +2-2 cos 
For small 
 Noise power at the output is then

41. FINITE OPAMP GAIN

42. EFFECT OF FINITE BANDWIDTH

43. EFFECT OF FINITE BANDWIDTH
Larger feedback factor  lower gain  faster setting
Settling determines maximum clock frequency
eg: CS = CF = 1pF   = 0.5
Assume u = 100 MHz
If we want setting to 1% error, time required  14.6ns  clock frequency = 34MHz.

44. TIME DOMAIN BEHAVIOUR
  Y[n] = Y [n-1] + (X[n-1] – V[n-1])
if Y[n]  0
Y[n] = 1.0
else Y[n] = - 1.0

45. It can be seen that the average value of the output is 1/3
TIME DOMAIN BEHAVIOUR
For example, for a DC input = , the time domain output for the first six clock cycles is given by:
Y[n]
V[n]
0.0 1
0.33 2
-0.33 -1 3 4 5 6
It can be seen that the average value of the output is 1/3

46. TIME DOMAIN BEHAVIOUR (Non Linear)
§ Quantization error spectrum is not white; successive output levels may be correlated.
§  Limit cycle oscillations that lead to tones in the output
eg. DC input X[n] = x
 For a limit cycle of period T;
V[n] = V[n+T]
 Y[n] = Y[n+T]
Since the input is DC, the input to the integrator will also be periodic.

47. TIME DOMAIN BEHAVIOUR (Non Linear)
Now Y[n] – Y[n-1] = X – V[n-1].
Write this equation for ‘T’ time instances and add; we get
but Y[T] = Y [0]

48. PATTERN NOISE IN  MODULATOR
It should be clear that the  MODULATOR is expected to give out the output equal to the DC input. Only limited no. of levels are allowed to the output , therefore output has to toggle from one level to another in order to keep average output equal to the DC input.
For eg. Input=0.5 Levels allowed are 0 and 1
Then the output will toggle between 0 and 1. If average is taken then the value of output of SDM is 0.5.
Therefore the output is oscillating with a frequency half of that of fs. That means in frequency domain the output will have tones at fs/2 and fs.

49. PATTERN NOISE IN  MODULATOR
Similarly for dc level of 1/256, the output will have, one one and 255 zeroes in 256 clocks (fs) this means the output will oscillate at a frequency of (fs/256). Hence it will have tones lying at multiples of this frequency. As the dc level comes closer to zero the tonal frequency decreases. The tones are completely harmless till they are out of the signal bandwidth.
The thing to note over here is that these tones represent noise as the information or signal is at 0 frequency rest of the frequency components are noise. This effect is very much prominent in I order modulators. Another important fact is that the amplitudes of the tones decrease as they come closer to the signal bandwidth. It is always better to analyze them by using simulations.

50. PATTERN NOISE IN  MODULATOR
The question to be asked is why are this tones dangerous in the signal bandwidth? The answer to this question lies in the fact that all the analysis made earlier on was based on the white noise approximation and the problem with the tones is that they are much above the expected noise floor. Hence the true signal to noise ratio is much lesser than what was expected from the analysis.

51. PATTERN NOISE IN  MODULATOR
It’s generally said that the pattern noise is visible only for slow moving inputs (not just DC). To understand this more clearly assume the input signal is a sinusoid with an input frequency of fm. If fm is a factor of fs then every time a new period of the sine wave starts the SDM will generate the same output as it generated in the earlier period. This means the output will also be changing with a frequency of fm. Hence the output will have tones at the harmonics of the input sinusoidal signal. If fm is very small then some of these harmonics will lie in signal bandwidth and the SNR will be lesser than expected.

52. PATTERN NOISE IN  MODULATOR
Pattern Noise Reduces Effective Bits.
The frequency domain output of the SDM shows tones and a noise floor. Consider them this noise to be made of two components 1. Tones 2. Random noise. Therefore in time domain these tones will give rise to impulses (if a large number of tones exist in the signal bandwidth). Since there is random noise, the impulse train will have a slightly varying magnitude but the frequency of repetition will be equal to the fundamental frequency. When these impulses are of the order of 2 or 3 LSBs. This means ENOB is lesser then was expected.

53. SECOND ORDER  MODULATOR
The 2nd order modulator has one delaying and one non-delaying integrator. Note that the last loop with the quantizer must have one unit of delay for stability. The z-domain transfer function of the second order modulator is given by:
Y(z) = z-1X(z) +(1-z-1)2 E(z)
NTF = (1-z-1)2

54. SECOND ORDER  MODULATOR
We can calculate the in band noise power of a second order  modulator to obtain
Giving us a noise figure of

55. SECOND ORDER  MODULATOR

56. INTEGRATOR OVERLOAD
In second order modulator with a single delaying integrator, simulations show that the maximum outputs of the two integrators increase as the signal level increase. Very often, they are several times the full scale analog input range. The following table contains data from simulations. The output levels indicated are the maximum levels at the output of the two integrators.

57. INTEGRATOR OVERLOAD
Input level (dB)
Ist integrator output level
2nd integrator level
-40
-20
-13.9
-10.45
-7.95
-6.02
-4.43
-3.09
-1.9
0.33
0.96
0.99
1.09
1.22
1.33
1.37
1.49
1.43
2.62
2.77
2.8
3.03
3.51
3.99
4.08
5.38
5.21
It is seen that the levels increase as the input value increases. This reduces the dynamic range of the modulation since the integrations will now saturate. The 2nd order modulator can be modified as follows:

58. INTEGRATOR OVERLOAD
The linearized transfer function is
Y(z) = X (z) . z-2 + (1 – z-1)2E(z)
The signal levels at the output of the integrators are now the following

59. INTEGRATOR OVERLOAD
Input level (dB)
Ist integrator output level
2nd integrator level
-40
-20
-13.9
-10.45
-7.95
-6.02
-4.43
-3.09
-1.9
0.33
0.96
0.99
1.09
1.22
1.33
1.37
1.49
1.43
2.62
2.77
2.8
3.03
3.51
3.99
4.08
5.38
5.21
       The signal levels at the first integrator output is reduced. However the second integrator output levels are still high.
§         The SNR in the two cases remains the same.
§         The circuit specifications are now more relaxed since there are two units of delay in the loop.

60. INTEGRATOR OVERLOAD
We need to reduce the output levels in the second integrator. For this we need to alter the gain just before the second integrator. Let us see the effect of altering this gain.

61. INTEGRATOR OVERLOAD
Clock cycle
Output 2 3 4 5 6 7 8 1 -1

62. INTEGRATOR OVERLOAD
Therefore, even though the linearized transfer function has changed, there is no change in the actual output. This is because we have a two level quantizer, the output of which depends only on the polarity and not the magnitude of the input. The quantizer effectively acts as an AGC and makes the overall gain 1.
The second integrator gain can be adjust to reduce the integrator output levels. Typically it is made less than one. For a gain of ½, the integrator output levels are the following

63. INTEGRATOR OVERLOAD Signal level (dB) Ist integrator output level
2nd integrator output level
-40
-20
-13.9
-10.45
-7.95
-6.02
-4.43
-3.09
-1.9
0.83
0.96
0.99
1.09
1.22
1.33
1.37
1.49
1.43
0.655
0.69
0.7
0.75
0.87
1.02
1.34
1.3

64. CIRCUIT NOISE
The sizes of the input capacitors should be chosen both on the basis of slow rate as well as thermal noise considerations. Thermal noise is basically introduced by non-zero resistance of the sampling switches.
The baseband component of this noise is approximately proportional to (kT/C)(1/OSR) where ‘C’ is the sampling capacitor. If the OSR = 256, C = 1pF , the noise power will be x Joules. The total quantization noise power in baseband at this OSR, with quantizer levels =  1 is 5.9 x Joules. Choose larger capacitance.

65. SAMPLING JITTER
Sampling Clock Jitter results in non uniform sampling, increasing total noise power in the quantizer output.
For a sinusoidal input with amplitude A and frequency fx

66. SAMPLING JITTER
If the jitter is assumed to be an uncorrelated Gaussain random process (‘white’), with standard deviation t, the average power of this error signal is
Since this is assumed to be white, the total error power in baseband is

67. IMPLEMENTATION IMPERFECTIONS
Supposing the two integrators have the following transfer functions

68. IMPLEMENTATION IMPERFECTIONS
Assume A1=A2 (the two opamp have the gain). Generally we can neglect the effect of the denominator and obtain NTF = (1 – z-1)2
(1-)4 is the unshaped noise, 2(1-)2  2 is the 1st order shaped noise and 2 4 is the 2nd order shaped noise.
 To make sure we get second shaped, we need A  OSR.

69. IMPLEMENTATION IMPERFECTIONS
Attenuation
Maximum Integrator Output levels
SNR (OSR = 256) Input = -20dB
0.9
5.98, 9.9 70
0.8
3.56, 4.26
83.15
0.7
2.05, 1.86
84.73
0.6
1.29, 0.9
83.59
0.5
0.962, 0.693
86.69
0.4
0.693, 0.625
86.71
0.3
0.510, 0.589
85.93
0.2
0.34, 0.562
77.45

70.  AD Converter

71. SIGNAL OUTPUTS OF  MODULATOR

72.  D/A CONVERTER
The sigma Delta D/A converter has a similar topology to the A/D converter. Here the input digital signal first goes through an interpolation filter, where it is upsampled and low pass filtered. After this it is fed to the modulator. The output of the modulator is a single bit signal, that comes at rate much higher than the Nyquist rate. The output of the modulator is ample and held and low pass filtered to give the analog output.

73.  D/A CONVERTER

74.  D/A CONVERTER
The input to the modulator is a 12 bit signal that is upsampled. The clock rate is much higher than the Nyquist rate. The modulator is a second order modulator and the topology is the same as the A/D converter. All numbers are in the 2’s complement form. A one bit quantizer in this case, would simple keep the MSB and throw out all the other bits. The D/D converter converts the one bit quantized output to 14 bit positive or negative number as shown.

75. AT LAST
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