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Fall 2002 Lecture 14: Instruction Scheduling. Saman Amarasinghe 26.035 ©MIT Fall 1998 Outline Modern architectures Branch delay slots Introduction to.

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Presentation on theme: "Fall 2002 Lecture 14: Instruction Scheduling. Saman Amarasinghe 26.035 ©MIT Fall 1998 Outline Modern architectures Branch delay slots Introduction to."— Presentation transcript:

1 Fall 2002 Lecture 14: Instruction Scheduling

2 Saman Amarasinghe 26.035 ©MIT Fall 1998 Outline Modern architectures Branch delay slots Introduction to instruction scheduling List scheduling Resource constraints Interaction with register allocation Scheduling across basic blocks Trace scheduling Scheduling for loops Loop unrolling Software pipelining 5

3 Saman Amarasinghe 36.035 ©MIT Fall 1998 Simple Machine Model Instructions are executed in sequence –Fetch, decode, execute, store results –One instruction at a time For branch instructions, start fetching from a different location if needed –Check branch condition –Next instruction may come from a new location given by the branch instruction

4 Saman Amarasinghe 46.035 ©MIT Fall 1998 Simple Execution Model 5 Stage pipe-line Fetch: get the next instruction Decode: figure-out what that instruction is Execute: Perform ALU operation –address calculation in a memory op Memory: Do the memory access in a mem. Op. Write Back: write the results back fetchdecodeexecutememorywriteback

5 Saman Amarasinghe 56.035 ©MIT Fall 1998 Simple Execution Model IF DEEXEMEMWB IF DEEXEMEMWB Inst 1 Inst 2 time

6 Saman Amarasinghe 66.035 ©MIT Fall 1998 Simple Execution Model IF DEEXEMEMWB IF DEEXEMEMWB Inst 1 Inst 2 time IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB Inst 1 Inst 2 Inst 3 Inst 4 Inst 5

7 Saman Amarasinghe 76.035 ©MIT Fall 1998 Outline Modern architectures Branch delay slots Introduction to instruction scheduling List scheduling Resource constraints Interaction with register allocation Scheduling across basic blocks Trace scheduling Scheduling for loops Loop unrolling Software pipelining 5

8 Saman Amarasinghe 86.035 ©MIT Fall 1998 Handling Cond. Branch Instructions Does not know the location of the next instruction until later –after DE in jump instructions –after EXE in branch instructions

9 Saman Amarasinghe 96.035 ©MIT Fall 1998 Handling Cond. Branch Instructions Does not know the location of the next instruction until later –after DE in jump instructions –after EXE in branch instructions IF DEEXEMEMWB Branch

10 Saman Amarasinghe 106.035 ©MIT Fall 1998 Handling Cond. Branch Instructions Does not know the location of the next instruction until later –after DE in jump instructions –after EXE in branch instructions IF DEEXEMEMWB IF DEEXEMEMWB Branch Inst

11 Saman Amarasinghe 116.035 ©MIT Fall 1998 Handling Cond. Branch Instructions Does not know the location of the next instruction until later –after DE in jump instructions –after EXE in branch instructions What to do with the middle 2 instructions? IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB Branch ??? Inst

12 Saman Amarasinghe 126.035 ©MIT Fall 1998 Handling Cond. Branch Instructions What to do with the middle 2 instructions? Stall the pipeline in case of a branch until we know the address of the next instruction –wasted cycles IF DEEXEMEMWB IF DEEXEMEMWB Branch Next inst

13 Saman Amarasinghe 136.035 ©MIT Fall 1998 Handling Cond. Branch Instructions What to do with the middle 2 instructions? Delay the action of the branch –Make branch affect only after two instructions –Two instructions after the branch gets executed regardless of the branch IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB Branch Next seq inst Branch target inst

14 Saman Amarasinghe 146.035 ©MIT Fall 1998 Branch Delay Slot(s) MIPS has a branch delay slot –The instruction after the branch gets executed if the branch gets executed –Fetching from the Branch target takes place only after that

15 Saman Amarasinghe 156.035 ©MIT Fall 1998 Branch Delay Slot(s) MIPS has a branch delay slot –The instruction after the branch gets executed if the branch gets executed –Fetching from the Branch target takes place only after that Branch delay slot ble r3, foo Branch delay slot

16 Saman Amarasinghe 166.035 ©MIT Fall 1998 Branch Delay Slot(s) MIPS has a branch delay slot –The instruction after the branch gets executed if the branch gets executed –Fetching from the Branch target takes place only after that Branch delay slot ble r3, foo Branch delay slot What to put in the branch delay slot?

17 Saman Amarasinghe 176.035 ©MIT Fall 1998 Filling The Branch Delay Slot Simple Solution: Put a no-op ble r3, foo Branch delay slot

18 Saman Amarasinghe 186.035 ©MIT Fall 1998 Filling The Branch Delay Slot Simple Solution: Put a no-op Wasted instruction, just like a stall ble r3, foo noop Branch delay slot

19 Saman Amarasinghe 196.035 ©MIT Fall 1998 Filling The Branch Delay Slot Move an instruction from above the branch ble r3, foo Branch delay slot

20 Saman Amarasinghe 206.035 ©MIT Fall 1998 Filling The Branch Delay Slot Move an instruction from above the branch moved instruction executes iff branch executes –Get the instruction from the same basic block as the branch –Don’t move a branch instruction! instruction need to be moved over the branch –branch does not depend on the result of the inst. prev_instr ble r3, foo prev_instr Branch delay slot

21 Saman Amarasinghe 216.035 ©MIT Fall 1998 Filling The Branch Delay Slot Move an instruction dominated by the branch instruction ble r3, foo dom_instr Branch delay slot foo: dom_instr

22 Saman Amarasinghe 226.035 ©MIT Fall 1998 Filling The Branch Delay Slot Move an instruction from the target –Instruction dominated by target –No other ways to reach target (if so take care of them) –If conditional branch, instruction should not have a lasting effect if the branch is not taken ble r3, foo instr Branch delay slot foo: instr

23 Saman Amarasinghe 236.035 ©MIT Fall 1998 Load Delay Slots Results of the loads is not available until end of MEM stage If the value of the load is used…what to do?? IF DEEXEMEMWB IF DEEXEMEMWB Load Use of load

24 Saman Amarasinghe 246.035 ©MIT Fall 1998 Load Delay Slots If the value of the load is used…what to do?? Always stall one cycle Stall one cycle if next instruction uses the value –Need hardware to do this Have a delay slot for load –The new value is only available after two instructions –If next inst. uses the register, it’ll get the old value IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB Load ??? Use of load

25 Saman Amarasinghe 256.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) r3 = *(r1 + 8) r4 = r2 + r3 r5 = r2 - 1 goto L1

26 Saman Amarasinghe 266.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) noop r3 = *(r1 + 8) noop r4 = r2 + r3 r5 = r2 - 1 goto L1 noop Assume 1 cycle delay on branches and 1 cycle latency for loads

27 Saman Amarasinghe 276.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) noop r3 = *(r1 + 8) noop r4 = r2 + r3 r5 = r2 - 1 goto L1 noop Assume 1 cycle delay on branches and 1 cycle latency for loads

28 Saman Amarasinghe 286.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) r3 = *(r1 + 8) noop r4 = r2 + r3 r5 = r2 - 1 goto L1 noop Assume 1 cycle delay on branches and 1 cycle latency for loads

29 Saman Amarasinghe 296.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) r3 = *(r1 + 8) noop r4 = r2 + r3 r5 = r2 - 1 goto L1 noop Assume 1 cycle delay on branches and 1 cycle latency for loads

30 Saman Amarasinghe 306.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) r3 = *(r1 + 8) noop r4 = r2 + r3 r5 = r2 - 1 goto L1 noop Assume 1 cycle delay on branches and 1 cycle latency for loads

31 Saman Amarasinghe 316.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) r3 = *(r1 + 8) r5 = r2 - 1 r4 = r2 + r3 goto L1 noop Assume 1 cycle delay on branches and 1 cycle latency for loads

32 Saman Amarasinghe 326.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) r3 = *(r1 + 8) r5 = r2 - 1 r4 = r2 + r3 goto L1 noop Assume 1 cycle delay on branches and 1 cycle latency for loads

33 Saman Amarasinghe 336.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) r3 = *(r1 + 8) r5 = r2 - 1 r4 = r2 + r3 goto L1 noop Assume 1 cycle delay on branches and 1 cycle latency for loads

34 Saman Amarasinghe 346.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) r3 = *(r1 + 8) r5 = r2 - 1 goto L1 r4 = r2 + r3 Assume 1 cycle delay on branches and 1 cycle latency for loads

35 Saman Amarasinghe 356.035 ©MIT Fall 1998 Example r2 = *(r1 + 4) r3 = *(r1 + 8) r5 = r2 - 1 goto L1 r4 = r2 + r3 Assume 1 cycle delay on branches and 1 cycle latency for loads

36 Saman Amarasinghe 366.035 ©MIT Fall 1998 Outline Modern architectures Branch delay slots Introduction to instruction scheduling List scheduling Resource constraints Interaction with register allocation Scheduling across basic blocks Trace scheduling Scheduling for loops Loop unrolling Software pipelining 5

37 Saman Amarasinghe 376.035 ©MIT Fall 1998 From a Simple Machine Model to a Real Machine Model Many pipeline stages –MIPS R4000 has 8 stages Different instructions taking different amount of time to execute –mult 10 cycles –div69 cycles –ddiv133 cycles Hardware to stall the pipeline if an instruction uses a result that is not ready

38 Saman Amarasinghe 386.035 ©MIT Fall 1998 Real Machine Model cont. Most modern processors have multiple execution units (superscalar) –If the instruction sequence is correct, multiple operations will happen in the same cycles –Even more important to have the right instruction sequence

39 Saman Amarasinghe 396.035 ©MIT Fall 1998 Instruction Scheduling Reorder instructions so that pipeline stalls are minimized

40 Saman Amarasinghe 406.035 ©MIT Fall 1998 Constraints On Scheduling Data dependencies Control dependencies Resource Constraints

41 Saman Amarasinghe 416.035 ©MIT Fall 1998 Data Dependency between Instructions If two instructions access the same variable, they can be dependent Kind of dependencies –True: write  read –Anti: read  write –Output: write  write What to do if two instructions are dependent. –The order of execution cannot be reversed –Reduce the possibilities for scheduling

42 Saman Amarasinghe 426.035 ©MIT Fall 1998 Computing Dependencies For basic blocks, compute dependencies by walking through the instructions Identifying register dependencies is simple –is it the same register? For memory accesses –simple: base + offset1 ?= base + offset2 –data dependence analysis: a[2i] ?= a[2i+1] –interprocedural analysis: global ?= parameter –pointer alias analysis: p1 ?= p

43 Saman Amarasinghe 436.035 ©MIT Fall 1998 Representing Dependencies Using a dependence DAG, one per basic block Nodes are instructions, edges represent dependencies

44 Saman Amarasinghe 446.035 ©MIT Fall 1998 Representing Dependencies Using a dependence DAG, one per basic block Nodes are instructions, edges represent dependencies 1: r2 = *(r1 + 4) 2: r3 = *(r1 + 8) 3: r4 = r2 + r3 4: r5 = r2 - 1

45 Saman Amarasinghe 456.035 ©MIT Fall 1998 Using a dependence DAG, one per basic block Nodes are instructions, edges represent dependencies 1: r2 = *(r1 + 4) 2: r3 = *(r1 + 8) 3: r4 = r2 + r3 4: r5 = r2 - 1 3 1 Representing Dependencies 2 4

46 Saman Amarasinghe 466.035 ©MIT Fall 1998 Using a dependence DAG, one per basic block Nodes are instructions, edges represent dependencies 1: r2 = *(r1 + 4) 2: r3 = *(r1 + 8) 3: r4 = r2 + r3 4: r5 = r2 - 1 Edge is labeled with Latency: –v(i  j) = delay required between initiation times of i and j minus the execution time required by i 3 1 Representing Dependencies 2 4 22 2

47 Saman Amarasinghe 476.035 ©MIT Fall 1998 Example 1: r2 = *(r1 + 4) 2: r3 = *(r2 + 4) 3: r4 = r2 + r3 4: r5 = r2 - 1 3 12 4 22 2 3

48 Saman Amarasinghe 486.035 ©MIT Fall 1998 Another Example 1: r2 = *(r1 + 4) 2: *(r1 + 4) = r3 3: r3 = r2 + r3 4: r5 = r2 - 1 3 12 4

49 Saman Amarasinghe 496.035 ©MIT Fall 1998 Another Example 1: r2 = *(r1 + 4) 2: *(r1 + 4) = r3 3: r3 = r2 + r3 4: r5 = r2 - 1 3 12 4 22 1 1

50 Saman Amarasinghe 506.035 ©MIT Fall 1998 Control Dependencies and Resource Constraints For now, lets only worry about basic blocks For now, lets look at simple pipelines

51 Saman Amarasinghe 516.035 ©MIT Fall 1998 Example 1: LAr1,array 2: LDr2,4(r1) 3: ANDr3,r3,0x00FF 4: MULCr6,r6,100 5: STr7,4(r6) 6: DIVCr5,r5,100 7: ADDr4,r2,r5 8: MULr5,r2,r4 9: STr4,0(r1)

52 Saman Amarasinghe 526.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1)

53 Saman Amarasinghe 536.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1

54 Saman Amarasinghe 546.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1

55 Saman Amarasinghe 556.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 12

56 Saman Amarasinghe 566.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 123

57 Saman Amarasinghe 576.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234

58 Saman Amarasinghe 586.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234

59 Saman Amarasinghe 596.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 5

60 Saman Amarasinghe 606.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56

61 Saman Amarasinghe 616.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56

62 Saman Amarasinghe 626.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 7

63 Saman Amarasinghe 636.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 7

64 Saman Amarasinghe 646.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 78

65 Saman Amarasinghe 656.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 789

66 Saman Amarasinghe 666.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 789 14 cycles!

67 Saman Amarasinghe 676.035 ©MIT Fall 1998 Outline Modern architectures Branch delay slots Introduction to instruction scheduling List scheduling Resource constraints Interaction with register allocation Scheduling across basic blocks Trace scheduling Scheduling for loops Loop unrolling Software pipelining 5

68 Saman Amarasinghe 686.035 ©MIT Fall 1998 List Scheduling Algorithm Idea –Do a topological sort of the dependence DAG –Consider when an instruction can be scheduled without causing a stall –Schedule the instruction if it causes no stall and all its predecessors are already scheduled Optimal list scheduling is NP-complete –Use heuristics when necessary

69 Saman Amarasinghe 696.035 ©MIT Fall 1998 List Scheduling Algorithm Create a dependence DAG of a basic block Topological Sort READY = nodes with no predecessors Loop until READY is empty Schedule each node in READY when no stalling Update READY

70 Saman Amarasinghe 706.035 ©MIT Fall 1998 Heuristics for selection Heuristics for selecting from the READY list –pick the node with the longest path to a leaf in the dependence graph –pick a node with most immediate successors –pick a node that can go to a less busy pipeline (in a superscalar)

71 Saman Amarasinghe 716.035 ©MIT Fall 1998 Heuristics for selection pick the node with the longest path to a leaf in the dependence graph Algorithm (for node x) –If no successors d x = 0 –d x = MAX( d y + c xy ) for all successors y of x –reverse breadth-first visitation order

72 Saman Amarasinghe 726.035 ©MIT Fall 1998 Heuristics for selection pick a node with most immediate successors Algorithm (for node x): –f x = number of successors of x

73 Saman Amarasinghe 736.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1)

74 Saman Amarasinghe 746.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 1: LAr1,array 2: LDr2,4(r1) 3: ANDr3,r3,0x00FF 4: MULCr6,r6,100 5: STr7,4(r6) 6: DIVCr5,r5,100 7: ADDr4,r2,r5 8: MULr5,r2,r4 9: STr4,0(r1)

75 Saman Amarasinghe 756.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3

76 Saman Amarasinghe 766.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0

77 Saman Amarasinghe 776.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3

78 Saman Amarasinghe 786.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3

79 Saman Amarasinghe 796.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7

80 Saman Amarasinghe 806.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4

81 Saman Amarasinghe 816.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5

82 Saman Amarasinghe 826.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0

83 Saman Amarasinghe 836.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { }

84 Saman Amarasinghe 846.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { } 1, 3, 4, 6

85 Saman Amarasinghe 856.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 6, 1, 4, 3 } 1, 3, 4, 6

86 Saman Amarasinghe 866.035 ©MIT Fall 1998 Example 1 6 8279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 6, 1, 4, 3 }

87 Saman Amarasinghe 876.035 ©MIT Fall 1998 Example 1 6 8279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 6, 1, 4, 3 } 6

88 Saman Amarasinghe 886.035 ©MIT Fall 1998 Example 1 6 8279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 1, 4, 3 } 6

89 Saman Amarasinghe 896.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 1, 4, 3 } 6

90 Saman Amarasinghe 906.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 1, 4, 3 } 61

91 Saman Amarasinghe 916.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 4, 3 } 61 2

92 Saman Amarasinghe 926.035 ©MIT Fall 1998 Example 1 6 8279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 2, 4, 3 } 61

93 Saman Amarasinghe 936.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 2, 4, 3 } 61

94 Saman Amarasinghe 946.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 2, 4, 3 } 61

95 Saman Amarasinghe 956.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 2, 4, 3 } 612

96 Saman Amarasinghe 966.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 4, 3 } 612 7

97 Saman Amarasinghe 976.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 612

98 Saman Amarasinghe 986.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 612

99 Saman Amarasinghe 996.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 612

100 Saman Amarasinghe 1006.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 612

101 Saman Amarasinghe 1016.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 6124

102 Saman Amarasinghe 1026.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3 } 6124 5

103 Saman Amarasinghe 1036.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3, 5 } 6124

104 Saman Amarasinghe 1046.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3, 5 } 6124

105 Saman Amarasinghe 1056.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3, 5 } 6124

106 Saman Amarasinghe 1066.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3, 5 } 61247

107 Saman Amarasinghe 1076.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 3, 5 } 61247 8, 9

108 Saman Amarasinghe 1086.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 3, 5, 8, 9 } 61247

109 Saman Amarasinghe 1096.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 3, 5, 8, 9 } 61247

110 Saman Amarasinghe 1106.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 3, 5, 8, 9 } 612473

111 Saman Amarasinghe 1116.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 5, 8, 9 } 612473

112 Saman Amarasinghe 1126.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 5, 8, 9 } 612473

113 Saman Amarasinghe 1136.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 5, 8, 9 } 612473

114 Saman Amarasinghe 1146.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 5, 8, 9 } 6124735

115 Saman Amarasinghe 1156.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 8, 9 } 6124735

116 Saman Amarasinghe 1166.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 8, 9 } 6124735

117 Saman Amarasinghe 1176.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 8, 9 } 6124735

118 Saman Amarasinghe 1186.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 8, 9 } 61247358

119 Saman Amarasinghe 1196.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 9 } 61247358

120 Saman Amarasinghe 1206.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 9 } 61247358

121 Saman Amarasinghe 1216.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 9 } 61247358

122 Saman Amarasinghe 1226.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 9 } 612473589

123 Saman Amarasinghe 1236.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { } 612473589

124 Saman Amarasinghe 1246.035 ©MIT Fall 1998 Example 612473589 Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 9 cycles

125 Saman Amarasinghe 1256.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 789 14 cycles Vs 9 cycles 612473589

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