4 2007 ITRS ChangesThe accelerated reduction of MPU gate length is driving requirements for improved and new metrology and yield management technology. CD is an example of a critical need that is challenging to meet. The present ITRS roadmap indicates that the process range for total CD variation is 10% of the gate length. This means that the precision becomes a difficult to reach value of 0.5 nm for the 65 nm node. A new requirement for line edge roughness comes from the rapid introduction of new resists/arc for 193 nm and 157 nm. Line edge roughness has been correlated to leakage current.Many people feel that a 20% process range is more representative of what is really found in manufacturing. As a result of not having CD capability with the precision, we bin chips for speed after the processing is done with much less than 100% yield for highest clock speed.
7 Courtesy of A. Ymaguchi (Hitachi) LER/LWR measurementTest method is approved as a SEMI standard in Nov./2006 andis available at SEMI homepageP ：“Test Method for Evaluation of Line-Edge Roughness and Linewidth Roughness”Suggested measurement parameters areMeasurement length L : 2um or longerSampling interval ⊿y : 10nm or lessOne of our collaboration resultsamong TWGs and related peopleΔy L0.2 um Courtesy of A. Ymaguchi (Hitachi)
8 3D Metrology Requirements example:Recess Channel Devicechallenges:complex grating-over-grating structureincludes overlay shift between the gratingsprofile/geometry in different orientations is relevantsmall profile features may be relevant (e.g. corner devices)AA 2D gratingtop view12RC 3D grating12Deep Trench pattern(not present in test structures)
9 3D Metrology Requirements overlay shiftcreates asymmetryperfect overlaycross section example
10 FEP Metrology: Expanded Emphasis on Areas beyond High k Increase in Mobility by using local stressing of transistors – FEP Call for local stress metrology in the channelMetal Gates in production – Is routine Work Function measurement is a new requirement?New transistor designs are advancing rapidly Example: FIN-FETs require 3D metrologyRapid annealing at 32/22 nm Generation will drive new dopant metrology needs & characterization of active carriers in transistors.
11 Proposal of new item on FEP table Local Strain/Stress MeasurementProposal of new item on FEP tableRelatively small laser spot(Visible light)with deeper penetrationpMOSnMOSGhani, et al (Intel)Wide laser spotfor extracting average stressMeasurement PointStress LinerSmall laser spotfor extracting single Tr. stressSTISTIChannelStrain/StressCross sectioningModified from Fichtner’s figure
12 New table for Local Strain/Stress Measurement need inputs from FEP and PIDS Table 120a Front End Processes Metrology Technology Requirements—Near-term YearsMobility Enhancement FactorFor Idsat (Table 40ab)- Extended Planar Bulk- UTB FDS- DGStress measurement with 50MPa resolutionSpatial resolution(Offline, destructive, single Tr.)1/5 of Gate Length54.422.214.171.124.62.22Spatial resolution(Inline, non-destructive,Test pattern for average stressmeasurement)Same size with HP655750454036322825Using test pad of 100um X 100um100Throughput (wafers/hour)(Inline, non-destructive,Test pattern)25 sites per wafer2
13 Local Strain/Stress Measurement Method (Tentative) SensitivityMeasurementAreaSampleThicknessArea of InterestStressStrainTransistor Level- CBED- NBD- TERS20 MPa100 MPa50 MPa0.02%0.1%0.05%10-20nm~10nm<50nm<100nm<300nmDestructiveDestructiveDestructiveNon-DestructiveMicro-Area Level- Confocal Raman- XRD- PhotoreflectanceSpectroscopy20 MPa10 MPa0.05%0.01%~150nm100umNon-DestructiveHandling Area of ITRSDie- Die level flatness- Laser Interferometry- Coherent Gradient SensingNon-DestructiveWafer- LaserInterferometry- CoherentGradient Sensing10 MPa0.001%waferNon-DestructiveTERS (Tip Enhanced Raman Scattering)CBED (Convergent Beam Electron Diffraction)NBD (Nano Beam Electron Diffraction)XRD (X-ray Diffraction)* Stress – Strain relation : need to be clarified
14 Trend : Use Modeling to connect what you can measure with what you need to know Example: Metrology of Strained Channel DevicesMD Giles, et. al., VLSI Symposium 2004
15 Dopant profile measurement (Essentially destructive) 2006 Update10nm10nm10nm1×1018atoms/cm3Dan Herr - SRCTotal throughput of analysis is one of remaining issuesDo we need to put in a throughput requirement?
16 Wrap Around Gate Metrology Side Wall and Top Dielectric Thickness and CompositionFINFETFINWrap Around Gate
18 2007 Interconnect Metrology Air Gap based “dielectric” near term potential solution for 22 nm ½ pitch ≠porous low kAir Gap sacrificial layer does not require unique metrologyMetrology is needed for 3D IntegrationAlignment of chips for stacking – wafer level integrationDefects in bondingDamage to metal layersDefects in vias between wafersThrough Si via is high aspect ratio CD issueMeasurements of Sidewall barrier thickness and sidewall damage (compositional changes in low k) after etch remains a Major Gap - It will soon also be a Gap for FEP MetrologyNew - Porous low k is projected for 32 nm ½ Pitch.
19 Metrology for Emerging Research Devices and Materials – 2007 ERM Teleconferences Atomic and nanoscale structure (including defects) of low Z materials, such as carbon nanotubes and graphitic materialsCorrelate nanostructure to macro-scale: bandgap, contact resistance, adhesion, mobility, dynamic properties, and nano-mechanical propertiesUniformity measurements of nanoscale properties over large areasIn-Situ measurements that enable enhanced synthetic and process controlAberration corrected HR-TEM of CNT with KIMetrology enablesunderstanding the effectof crystal twins onmobility and mechanical properties
20 Excitons dominate E1 transitions Metrology for Emerging Research Devices and Materials – 2007 ERM TeleconferencesExcitons dominate E1 transitionsFor 1.2 nm Si NanowiresYang, PRB 75 (2007)Nondestructive 3D imaging of embedded interface, nanostructure, and atomic scale matrix propertiesOptical properties of isolated and integrated low dimensional materialsMethods that resolve and separate surface from bulkIntegrated metrology and modeling tools that deconvolve probe - sample interactionsNanoparticle monitors for ES&H,which include size, dose, and composition.
21 Metrology Key Messages Litho MetrologyDual Patterning Overlay MetrologyOverlay Metrology Capability for Single Layer in RED for 45 nm ½ pitchOverlay Definition for 32 nm ½ Pitch?Tightened to 70% of single layerChallenge of High Aspect Ratio Contact Hole MetrologySEMI Standard for LER / LWR acceptedWafer Sampling Methodology Section addedNew Uncertainty Definition- replace PrecisionMain challenge to CD Metrology before 32 nm ½ pitch is tool matching3D Dimensional and Shape Metrology for FEP, Interconnect and Litho
22 Metrology Key Messages FEP MetrologyStress/Strain Metrology Requirements added in 20072D/3D Dopant Profiling turn around time requirement added in 2007Interconnect Metrology3D Interconnect Metrology added in 2007
23 Conclusions CD Measurement improvements show a path to the 32 nm Node Propose definition for LWR and including LERTransistor channel engineering requires Stress and Mobility MeasurementInterconnect requires Sidewall Measurements for barrier/seed and low trenchERM and ERD require both improved imaging (such as aberration corrected TEM) and image simulation