6 Lithography Metrology for Advanced Patterning SpacerPatterningDoubleExposureDoublePatterning2pCD p/2SpacersMetrology Need:Latent Image CDCD-AFM after both exposures but no Solution for CD between exposuresMetrology Need:Overlay withPrecision of 70%Of Single LayerMetrology Need:Spacer Thickness on SidewallSpacer Profile22 nm Dense lines
7 Impact of Process on Metrology : courtesy Litho TWG Loading effects of etching and CVD depend on not only pattern environment but resist pattern shape. So the shape itself is important requirement of metrology.Requirements of shape should cover not only top CD, bottom CD, height and SWA, but 2D(or 3D) structure.
8 Metrology Challenges for Advanced Litho Processes 2 Population CD, SWA, height and pitchPotential Solution -> scatterometryQ: is there enough sensitivity for odd-even line scenarioMetrology for Latent Image at 1st exposuremight be avoided usingAEC/APC approaches & CD/Overlayafter double exposure
9 3D Metrology Requirements overlay shiftcreates asymmetryperfect overlaycross section example
10 New FEP Metrology Requirements for Ultimately Scaled and Functionally Enhanced CMOS: Non-Destructive local strain/stress measurementDopant activation Metrology for USJInterface MetrologyNew channel material or structures challengesSiGe & III-VTrigate FinFET, NanowireCarbon nanotubes & GrapheneSurface/film analysis on vertical surfacesIn-situ monitoring of multi-component oxidesIn-Line work function measurements – band gap engineering for flash and gatesActive depth profile: what percentage of the implanted atoms/ions is electrically active?FEP wants to measure particles and composition on bare silicon wafers and on in-process wafers down to 20nm size - non-destructive with high productivity
11 Proposal of new item on FEP table Local Strain/Stress MeasurementProposal of new item on FEP tableRelatively small laser spot(Visible light)with deeper penetrationpMOSnMOSGhani, et al (Intel)Wide laser spotfor extracting average stressMeasurement PointStress LinerSmall laser spotfor extracting single Tr. stressSTISTIChannelStrain/StressCross sectioningModified from Fichtner’s figure
12 New table for Local Strain/Stress Measurement need inputs from FEP and PIDS Table 120a Front End Processes Metrology Technology Requirements—Near-term YearsMobility Enhancement FactorFor Idsat (Table 40ab)- Extended Planar Bulk- UTB FDS- DGStress measurement with 50MPa resolutionSpatial resolution(Offline, destructive, single Tr.)1/5 of Gate Length54.4126.96.36.199.62.22Spatial resolution(Inline, non-destructive,Test pattern for average stressmeasurement)Same size with HP655750454036322825Using test pad of 100um X 100um100Throughput (wafers/hour)(Inline, non-destructive,Test pattern)25 sites per wafer2
13 Local Strain/Stress Measurement Method (Tentative) SensitivityMeasurementAreaSampleThicknessArea of InterestStressStrainTransistor Level- CBED- NBD- TERS20 MPa100 MPa50 MPa0.02%0.1%0.05%10-20nm~10nm<50nm<100nm<300nmDestructiveDestructiveDestructiveNon-DestructiveMicro-Area Level- Confocal Raman- XRD- PhotoreflectanceSpectroscopy20 MPa10 MPa0.05%0.01%~150nm100umNon-DestructiveHandling Area of ITRSDie- Die level flatness- Laser Interferometry- Coherent Gradient SensingNon-DestructiveWafer- LaserInterferometry- CoherentGradient Sensing10 MPa0.001%waferNon-DestructiveTERS (Tip Enhanced Raman Scattering)CBED (Convergent Beam Electron Diffraction)NBD (Nano Beam Electron Diffraction)XRD (X-ray Diffraction)* Stress – Strain relation : need to be clarified
14 Trend : Use Modeling to connect what you can measure with what you need to know Example: Metrology of Strained Channel DevicesMD Giles, et. al., VLSI Symposium 2004
15 Dopant profile measurement (Essentially destructive) 2008 Update10nm10nm10nm1×1018atoms/cm3Dan Herr - SRCTotal throughput of analysis is one of remaining issuesDo we need to put in a throughput requirement?What percentage of the atoms/ions is electrically active?
16 Wrap Around Gate Metrology Side Wall and Top Dielectric Thickness and CompositionFINFETFINWrap Around Gate
18 2008 Interconnect Metrology Existing ChallengesMeasurements of Sidewall barrier thickness and continuitySidewall damage (compositional changes, densification and defect formation in low k) after etch remains a Major Gap - It will soon also be a Gap for FEP MetrologyCharacterization of pores, pore size distribution, and topologyDetection of Voids after electroplatingMonolayer interface for new barrier-low kAir Gap sacrificial layer does not require unique metrologyMetrology is needed for 3D IntegrationTSV Depth and Profile through multiple layersAlignment of chips for stacking – wafer level integrationBond strengthDefects in bonding: un-bonded regionsDamage to metal layers; e.g., scratches which could result in voidsDefects in vias between wafersCD determination of high aspect for Si viasWafer thickness and TTV after thinningDefects after thinning including wafer edgeCharacterization of the edge of grapheneTSV Through Silicon ViaTTV Total Thickness Variation
19 ERD/Metrology Collaboration Discussion Small geometrical metrologies, obtaining a reasonable signal/noise ratio – study, determine, and manage noise sources. Extract the signal from noise.Issue of contamination of nano-scaled devicesTime resolved magnetic measurements.Ability to perform real time measurements, e.g. phase transitions.Wide band characterizations of rf devices – above 100 GHz.Questions from MetrologyPCM – Near mfg?MRAM – In production? Spin torque RAMContamination -A requirements table is needed for on-line, in-line, and off-line metrology
20 Metrology Summary FEP-Interconnect-Litho ERD-ERM High K changes 3D Metrology – Confirm Geometry Requirementse.g. film thickness on sidewallReference Methods for 3DStress – e.g. buried channelsERD-ERMProperties of low Dimensional MaterialsMicroscopy and feature size/functionTime resolved magnetic measurementsAbility to perform real time measurements,e.g. phase transitionsHigh K changesLitho scaling& Metrology
21 ConclusionsCD Measurement improvements show a path to the 32/22 nm ½ PitchTransistor channel engineering requires Stress and Mobility MeasurementInterconnect requires Sidewall Measurements for barrier/seed and low trenchERM and ERD require both improved imaging (such as aberration corrected TEM) and image simulationDetermination of not only atomic composition of layers, but electrical activity of those atoms/ions
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