Presentation on theme: "ITRS Winter Conference 2007 Kamakura, Japan 1 International Technology Roadmap for Semiconductors Assembly and Packaging 2007."— Presentation transcript:
ITRS Winter Conference 2007 Kamakura, Japan 1 International Technology Roadmap for Semiconductors Assembly and Packaging 2007
ITRS Winter Conference 2007 Kamakura, Japan 2 Assembly and Packaging Roadmap 2007 Participants W. R. Bottoms, Chair William Chen, Co-chair John Hunt Mike Hung, Ph.D Sreenivasan Koduri Li Rongshen Lee Dongho Lee David Love Mike Lamson HeeSoo Lee Choon Heung Lee Sebastian Liau Hongwei Liang Weichung Lo Michitaka Kimura Debendra Mallik Lei Mercado Stan Mihelcic Abhay Maheshwari Gary Morrison Jean-Pierre Moscicki Hikari Murai Rajen Murugan Manoj Nagulapally Hirofumi Nakajima Keith Newman Luu Nguyen Dick Otte Masashi Otsuka Bob Pfahl Ralf Plieninger Klaus Pressel Marc Petersen Gilles Poupon Charles Richardson Bernd Roemer Bill Reynolds Bidyut Sen Yong-Bin Sun Coen Tak Henry Utsunomiya Shoji Uegaki David Walter Lawrence Williams M. Juergen Wolf Jie Xue Zhiping Yang, Ph.D. Edgar Zuniga Seiichi Abe Joseph Adam Mudasir Ahmad Bernd Appelt Ivor Barber Muhannad Bakir Mario Bolanos-Avila Craig Beddinfield Kwang Yoo Byun Carl Chen Chi Chi Chang Bob N. Chylak Sonjin Cho Jason Cho Chetan Desai Kishor Desai Darvin Edwards John T. "Jack" Fisher Darrell Frear George Harman Ryo Haruta Harry Hedler Harold Hosack
ITRS Winter Conference 2007 Kamakura, Japan 3 ITRS A&P Chapter Organization This Chapter is organized in eight major sections: Difficult Challenges Single Chip Packaging Wafer Level Packaging System-in-Package Packaging for Specialized Functions Advanced Packaging Technologies Equipment Requirements Cross-Cut Issues
ITRS Winter Conference 2007 Kamakura, Japan 4 Packaging Technology Challenges Interconnect Scaling Connect Si features (nm) to circuit board features (cm) Power Delivery Efficiently deliver Power to enable high speed Si performance Power Removal Efficiently duct away dissipated power High Speed Signaling Facilitate distortion – free signaling
ITRS Winter Conference 2007 Kamakura, Japan 5 Assembly and Packaging Difficult Challenges Pb free transition presents cost, reliability and process compatibility problems that are not yet fully resolved A new generation of DFM & DFT solutions will be required for complex SiP, SoC 3D packaging Thermal issues for complex 3D packaging Stress induced changes in electrical properties for very thin die Reliability for through wafer vias and die layer bonding Warpage control for stacked die Interconnect for nano-scale structures Handling of ultra thin die and self assembly for very small die
ITRS Winter Conference 2007 Kamakura, Japan 6 The Pace of Change in Packaging is Accelerating As traditional CMOS scaling nears it natural limits other technologies are needed to continue progress This has resulted in an increase in the pace of innovation. Many areas has outpaced ITRS Roadmap forecasts. Among these are: Wafer thinning and handling of thinned wafers/die Wafer level packaging Incorporation of new materials 3D integration The consumerization of electronics is the primary driving force.
ITRS Winter Conference 2007 Kamakura, Japan 7 Consumer Markets Drive Innovation Consumers now drive more than half of integrated circuit revenue Assembly and Packaging technology is a primary differentiator for consumer electronics These factors are driving an unprecedented pace of innovation in: New Materials New Technologies New Systems Integration architecture
ITRS Winter Conference 2007 Kamakura, Japan 8 New Packaging Technologies Thinned wafers 3D systems integration Wafer level packaging Bio-chips Integrated optics Embedded/integrated active and passive devices MEMS Flexible (wearable) electronics Printable circuits Semiconductors Light emitters RF Interconnect Texflex embroidered interconnects (Fraunhofer IZM)
ITRS Winter Conference 2007 Kamakura, Japan 9 Wafer Thinning Table 102a&b Thinned Silicon Wafer Thickness 200 mm/300 mm Year of Production Min. thickness of thinned wafer (microns) (general product) Min. thickness of thinned wafer (microns) (For extreme thin package ex. Smart card) * It was easier than we thought. Handling of Thinned wafers and die will be the limiting factor
ITRS Winter Conference 2007 Kamakura, Japan 10 Wafer Level Packaging One of the fastest growing packaging architectures WLP offers portable consumer products : inherent lower cost improved electrical performance lower power requirements Smaller size Several architectural variations are in use today
ITRS Winter Conference 2007 Kamakura, Japan 11 Applications for New Materials In this decade most if not all packaging materials will change due to changing functional and regulatory requirements Bonding wire Molding compounds Underfill Thermal interface materials Die attach materials Substrates Solder
ITRS Winter Conference 2007 Kamakura, Japan 12 New Materials Cu interconnect Ultra Low k dielectrics High k dielectrics Organic semiconductors Green Materials Pb free Halogen free Many are in use today Many are in development Nanotubes Nano Wires Macromolecules Nano Particles Composite materials
ITRS Winter Conference 2007 Kamakura, Japan 13 Through Silicon Vias (TSV) A Key technology for both wafer level packaging and 3D integration From front side From back side
ITRS Winter Conference 2007 Kamakura, Japan 14 System in Package (SiP) The next step in Assembly and Packaging: Systems Level Integration Introduction & Motivation The basic elements generic to all SiP System level integration applications will be defined. Examples will be used from various application areas to show how the basic elements are incorporated into these applications.
ITRS Winter Conference 2007 Kamakura, Japan 15 SiP: Multi-level System Integration Source: Fraunhofer IZM Packages may include: Sub-system packages Stacked thin packages including WLP, passives and active chips Mechanical, optical and other non electrical functions Complete systems or sub-systems with embedded components Bare die SiP may include SoC and other traditional packages
ITRS Winter Conference 2007 Kamakura, Japan 16 Categories of SiP PiP, PoP and more
ITRS Winter Conference 2007 Kamakura, Japan 17 3D Packaging increases Performance Density and enables system level integration New System in Package (SIP) solutions enables rapid integration of different functions Thru-Si via Stacking Sibley Spacer 256M NAND Sibley Wire bonded stacked die Small form factor for ultramobile PCs, hand-helds, phones & other consumer electronics
ITRS Winter Conference 2007 Kamakura, Japan 18 3D Integration Table 101 System-in-a-Package Requirements Year of Production Number of terminalslow cost handheld Number of terminalshigh performance (digital) Number of terminalsmaximum RF 200 Low cost handheld / #die / stack* high performance / die / stack Low cost handheld / #die / SiP high performance / #die / SiP Minimum TSV pitch TSV maximum aspect ratio** 10.0 TSV exit diameter(um) TSV layer thickness for minimum pitch Minimum component size (micron) x x x100
ITRS Winter Conference 2007 Kamakura, Japan 19 3D System Integration & Packaging Stacked functional Layers with TSV and /or flexible polymer Interposer
ITRS Winter Conference 2007 Kamakura, Japan 20 3D Stacked Die Package Samsung TSV 35 micron thick TSV of Tezzaron TSV of Ziptronix Elpida (Poly-Si TSV)
ITRS Winter Conference 2007 Kamakura, Japan 21 Stacked die SiP packages 2014 through 2020 Limited by thermal density
ITRS Winter Conference 2007 Kamakura, Japan 22 Substrate thickness: 0.16 Ball pitch: 0.8 mm 1.0 Mold resin thickness on top of die: 0.10 mm Die attach thickness TSV 0.025mm Embedded Typical SiP in 2010
ITRS Winter Conference 2007 Kamakura, Japan 23 Interconnect Challenges for Complex SiPs Evolutionary and revolutionary interconnect technologies are needed to enable the migration of microsystems from conventional state-of-art to 3D SiP. New circuit elements and components place expanded demands on the environment provided by the package
ITRS Winter Conference 2007 Kamakura, Japan 24 Interconnect Requirements may be satisfied by Optical Wave Guide Solutions Examples of guided wave optical interconnects for chip-to-chip interconnection.
ITRS Winter Conference 2007 Kamakura, Japan 25 Low k Dielectric will Require Low Stress IO Interconnections Si die Innovations in low stress electrical I/O can potentially eliminate the need for underfill reducing cost and processing complexity as I/O density rises.
ITRS Winter Conference 2007 Kamakura, Japan 26 SiP presents new challenges for Thermal management High performance and form factor reduction generate high thermal density Heat removal requires much greater volume than the semiconductor Increased volume means increased wiring length causing higher interconnect latency, higher power dissipation, lower bandwidth, and higher interconnect losses These consequences of increased volume generates more heat to restore the same performance ITRS projection for 14nm node Power density >100W/cm2 Junction to ambient thermal resistance <0.2degrees C/W
ITRS Winter Conference 2007 Kamakura, Japan 27 Thermofluidic Heat Sinks may be the Solution Examples of thermofluidic cooling integration with CMOS technology
ITRS Winter Conference 2007 Kamakura, Japan 28 Summary Packaging innovation enables More than Moore 3D packaging technologies Equivalent scaling through functional diversity Consumer market demands drive innovation in packaging Size, power, cost, performance, time to market New materials and architectures are required to meet todays market demand but will enable many future advances in packaging