Presentation on theme: "International Technology Roadmap for Semiconductors"— Presentation transcript:
1 International Technology Roadmap for Semiconductors Assembly and Packaging2007
2 Assembly and Packaging Roadmap 2007 Participants W. R. Bottoms, Chair William Chen, Co-chairSeiichi AbeJoseph AdamMudasir AhmadBernd AppeltIvor BarberMuhannad BakirMario Bolanos-AvilaCraig BeddinfieldKwang Yoo ByunCarl ChenChi Chi ChangBob N. ChylakSonjin ChoJason ChoChetan Desai Kishor DesaiDarvin EdwardsJohn T. "Jack" FisherDarrell Frear George HarmanRyo HarutaHarry Hedler Harold HosackJohn HuntMike Hung, Ph.DSreenivasan Koduri Li LiRongshen LeeDongho LeeDavid LoveMike Lamson HeeSoo Lee Choon Heung LeeSebastian LiauHongwei Liang Weichung LoMichitaka KimuraDebendra MallikLei MercadoStan MihelcicAbhay MaheshwariGary Morrison Jean-Pierre MoscickiHikari MuraiRajen MuruganManoj Nagulapally Hirofumi NakajimaKeith NewmanLuu NguyenDick OtteMasashi OtsukaBob PfahlRalf PlieningerKlaus PresselMarc Petersen Gilles PouponCharles RichardsonBernd RoemerBill ReynoldsBidyut SenYong-Bin SunCoen TakHenry UtsunomiyaShoji UegakiDavid Walter Lawrence WilliamsM. Juergen WolfJie XueZhiping Yang, Ph.D.Edgar Zuniga
3 ITRS A&P Chapter Organization This Chapter is organized in eight major sections:Difficult ChallengesSingle Chip PackagingWafer Level PackagingSystem-in-PackagePackaging for Specialized FunctionsAdvanced Packaging TechnologiesEquipment RequirementsCross-Cut Issues
4 Packaging Technology Challenges Interconnect ScalingConnect Si features (nm) to circuit board features (cm)High Speed SignalingFacilitate distortion –free signalingPower DeliveryEfficiently deliver Power to enable high speed Si performancePower RemovalEfficiently duct away dissipated power
5 Assembly and Packaging Difficult ChallengesPb free transition presents cost, reliability and process compatibility problems that are not yet fully resolvedA new generation of DFM & DFT solutions will be required for complex SiP, SoC 3D packagingThermal issues for complex 3D packagingStress induced changes in electrical properties for very thin dieReliability for through wafer vias and die layer bondingWarpage control for stacked dieInterconnect for nano-scale structuresHandling of ultra thin die and self assembly for very small die
6 The Pace of Change in Packaging is Accelerating As traditional CMOS scaling nears it natural limits other technologies are needed to continue progressThis has resulted in an increase in the pace of innovation.Many areas has outpaced ITRS Roadmap forecasts. Among these are:Wafer thinning and handling of thinned wafers/dieWafer level packagingIncorporation of new materials3D integrationThe consumerization of electronics is the primary driving force.
7 Consumer Markets Drive Innovation Consumers now drive more than half of integrated circuit revenueAssembly and Packaging technology is a primary differentiator for consumer electronicsThese factors are driving an unprecedented pace of innovation in:New MaterialsNew TechnologiesNew Systems Integration architecture
8 New Packaging Technologies Thinned wafers3D systems integrationWafer level packagingBio-chipsIntegrated opticsEmbedded/integrated active and passive devicesMEMSFlexible (wearable) electronicsPrintable circuitsSemiconductorsLight emittersRFInterconnectTexflex embroidered interconnects (Fraunhofer IZM)
9 Wafer Thinning It was easier than we thought. Table 102a&b Thinned Silicon Wafer Thickness 200 mm/300 mmYear of Production200720082009201020112012201320142015Min. thickness of thinned wafer (microns) (general product)504540Min. thickness of thinned wafer (microns) (For extreme thin package ex. Smart card)*2015108Handling of Thinned wafers and die will be the limiting factor
10 Wafer Level Packaging One of the fastest growing packaging architecturesWLP offers portable consumer products :inherent lower costimproved electrical performancelower power requirementsSmaller sizeSeveral architectural variations are in use today
11 Applications for New Materials In this decade most if not all packaging materials will change due to changing functional and regulatory requirementsBonding wireMolding compoundsUnderfillThermal interface materialsDie attach materialsSubstratesSolder
12 Many are in development New MaterialsMany are in use todayMany are in developmentCu interconnectUltra Low k dielectricsHigh k dielectricsOrganic semiconductorsGreen MaterialsPb freeHalogen freeNanotubesNano WiresMacromoleculesNano ParticlesComposite materials
13 Through Silicon Vias (TSV) From front sideFrom back sideA Key technology for both wafer level packaging and 3D integration
14 System in Package (SiP) “The next step in Assembly and Packaging: System in Package (SiP) “The next step in Assembly and Packaging: Systems Level Integration”Introduction & MotivationThe basic elements generic to all SiP System level integration applications will be defined.Examples will be used from various application areas to show how the basic elements are incorporated into these applications.
15 SiP: Multi-level System Integration SiP may include SoC and other traditional packagesPackages may include:Sub-system packagesStacked thin packages including WLP, passives and active chipsMechanical, optical and other non electrical functionsComplete systems or sub-systems with embedded componentsBare dieSource: Fraunhofer IZM
17 3D Packaging increases Performance Density and enables system level integration New System in Package (SIP) solutions enables rapid integration of different functionsSibleySpacer256M NANDWire bonded stacked dieConverged computing and communications devices more performance per mm3.More Mbits, More MIPS in shrinking volumetric dimensionsThru-Si via StackingSmall form factor for ultramobile PCs, hand-helds, phones & other consumer electronics
18 3D Integration Table 101 System-in-a-Package Requirements Year of Production200720082009201020112012201320142015Number of terminals—low cost handheld700800Number of terminals—high performance (digital)305031903350350936843860405342464458Number of terminals—maximum RF200Low cost handheld / #die / stack*7891011121314high performance / die / stack345Low cost handheld / #die / SiPhigh performance / #die / SiP6Minimum TSV pitch10.08.06.05.04.03.83.63.43.3TSV maximum aspect ratio**TSV exit diameter(um)3.02.52.01.18.104.22.168TSV layer thickness for minimum pitch502015Minimum component size (micron)1005600x300400x200200x100
19 3D System Integration & Packaging Stacked functional Layers with TSV and /or flexible polymer Interposer
20 3D Stacked Die Package TSV of Tezzaron TSV of Ziptronix Samsung TSV 35 micron thickElpida (Poly-Si TSV)
21 Stacked die SiP packages 2014 through 2020 Limited by thermal density
22 Mold resin thickness on top of die: 0.10 mm Typical SiP in 2010TSV0.025mmMold resin thickness on top of die: 0.10 mm● ● ● ●1.0Substrate thickness: 0.16● ● ● ● ● ● ● ●Die attach thickness 0.015Ball pitch: 0.8 mmEmbedded
23 Interconnect Challenges for Complex SiPs New circuit elements and components place expanded demands on the environment provided by the packageEvolutionary and revolutionary interconnect technologies are needed to enable the migration of microsystems from conventional state-of-art to 3D SiP.
24 Interconnect Requirements may be satisfied by Optical Wave Guide Solutions Solder bumpDieMirrorVCSEL/PDSubstratePolymer pinLensFiberBoard-level integrated optical devicesFiber-to-the-chipQuasi free-spaceoptical I/OLens assisted quasi free-space optical I/OSurface-normal optical waveguide I/OOpticalsource/PDExamples of guided wave optical interconnectsfor chip-to-chip interconnection.
25 Low k Dielectric will Require Low Stress IO Interconnections Si dieInnovations in low stress electrical I/O can potentially eliminate the need for underfill reducing cost and processing complexity as I/O density rises.
26 SiP presents new challenges for Thermal management High performance and form factor reduction generate high thermal densityHeat removal requires much greater volume than the semiconductorIncreased volume means increased wiring length causing higher interconnect latency, higher power dissipation, lower bandwidth, and higher interconnect lossesThese consequences of increased volume generates more heat to restore the same performanceITRS projection for 14nm nodePower density >100W/cm2Junction to ambient thermal resistance <0.2degrees C/W
27 Thermofluidic Heat Sinks may be the Solution Conventionalthermal InterconnectsBack-side integratedfluidic heat sink andBack and front-sideinlets/outletsThermal interface Materialfluidic heat sink usingTIM and inlets/outletstubeDiefluidic I/OExamples of thermofluidic cooling integration with CMOS technology
28 Summary Packaging innovation enables “More than Moore” 3D packaging technologiesEquivalent scaling through functional diversityConsumer market demands drive innovation in packagingSize, power, cost, performance, time to marketNew materials and architectures are required to meet today’s market demand but will enable many future advances in packaging