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1 ORTC 2012/13 ITRS Work IRC and CTSG Plenary Alan Allan 04/23/2012 Based on [WAS] ORTC Final Rev 1a, 12/13/11 [plus backup] CORRECTED/ UPDATED 04/23/12.

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Presentation on theme: "1 ORTC 2012/13 ITRS Work IRC and CTSG Plenary Alan Allan 04/23/2012 Based on [WAS] ORTC Final Rev 1a, 12/13/11 [plus backup] CORRECTED/ UPDATED 04/23/12."— Presentation transcript:

1 1 ORTC 2012/13 ITRS Work IRC and CTSG Plenary Alan Allan 04/23/2012 Based on [WAS] ORTC Final Rev 1a, 12/13/11 [plus backup] CORRECTED/ UPDATED 04/23/12 FOR 2012 IRC & CTSG WORK to prepare for 2013 ITRS

2 2 1)Unchanged for 2010/11: MPU contacted M1 1)2-year cycle trend through 2013 [27nm (14nm node)]; then 3-year trend to 2026 consider for 2013 ITRS proposal: extend 2yr cycle to 2017/14nm (7nm node) 2)60f 2 SRAM 6t cell Design Factor Proposal for 2013 ITRS consideration: tbd 3)175f 2 Logic Gate 4t Design Factor Proposal for 2013 ITRS consideration: tbd 4)Ongoing - evaluate alignment of nodes with latest M1 industry status and also High Performance/Low Power timing needs 2)Unchanged for 2010/11 Tables: MPU Functions/Chip and Chip Size Models 1)Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and cell design factors 2)ORTC line item OverHead (OH) area model, includes non-active area 3)Proposal for 2013 ITRS consideration: tbd; based on final consensus of new proposals 3)Updated for 2010/11 Tables: MPU GLpr, GLph – trends smoothed by PIDS modeling; but close to previous targets Proposal for 2013 ITRS consideration: tbd; targeted for 8% CAGR (1/CV/I) intrinsic transistor performance vs. present 2011 ITRS 13% trend 4)Updated for 2010/11 Tables: Vdd Low operating and standby line items from PIDS model track smoothed gate length changes Proposal for 2013 ITRS consideration: tbd; targeted for 8% CAGR (1/CV/I) intrinsic transistor performance vs. present 13% 5)Added in 2011 – Table ORTC-6 Battery Energy Storage (Watt-hours) Line Item from iNEMI Roadmap [will update based on 2013 iNEMI roadmap work] 2011 Renewal ITRS ORTC Technology Trend Pre-Summary [and including updates for 2012 Proposals and 2013 ITRS Renewal Preparation]

3 3 6)Updated in ORTC 2011 Tables - DRAM contacted M1: 1)1-year pull-in of M1 and bits/chip trends; [unchanged] 2)no Flattening of DRAM M1 as with Flash Poly** [unchanged] 3)4f2 push out [to 2013]; 2012 Update: 2014/4f2 4)Increased array efficiency from 56% to 59% [unchanged; needs review] 7)Updated in ORTC 2011 Tables - Flash Un-contacted Poly: 1)2+-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs) trend to 2020/10nm; then 3-year trend to 2022/8nm; then Flat Poly after 2022/8nm; [unchanged] 2)and 3bits/cell extended to 2018; 4bits/cell delay to 2022 [unchanged] 8)Updated in ORTC 2011 Tables - DRAM Bits/Chip and Chip Size Model: 1)3-year generation Moores Law bits/chip doubling cycle target (1-2yr delay for smaller chip sizes <30mm2 – 2x/2.5yrs) [unchanged] 9)Updated in ORTC 2011 Tables - Flash Bits/Chip and Chip Size Model: 1)3-year generation Moores Law bits/chip doubling cycle target (after 1-yr acceleration; then 1-2Tbits; keep chip size <160mm2); [unchanged] 2)New 3D layers Models vs. relaxed half-pitch tradeoffs are now included in the 2011 Renewal for maximum bits per chip [2012 Update Survey Proposal: 2016 increased from 8/32nm -128/18nm Layers to 16/48nm – 128/24nm Layers (option C in 2011 ORTC Table 2)] 2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)

4 4 10) Updated in ORTC 2011 Tables - ORTC Table 5 - Litho # of Mask Counts MPU, DRAM, 1) Flash Survey inputs Updated 2)Also IC Knowledge (ICK) model contribution to extend mask levels range 3)Proposal for 2013 ITRS consideration: tbd; based on survey plus modeling consensus of Litho, PIDS, FEP, Design 11) Unchanged for 2011[and 2012 Update] - IRC 450mm Position: 1)Timing Status (as of July, 2011 – to be updated by G450C in July, 2012) 1)Consortia work underway 2)IDM and Foundry Pilot lines: ; 3)Production: )SEMATECH/ISMI making good progress on 450mm program activities to meet the ITRS Timing 1) Consortium operations are using 450mm early test wafer process, metrology and patterning capability to support Supplier development 2)193 immersion multiple exposure litho tools are under development to support consortium and manufacturers schedules [for stated 1xnm technology goal; note: 19nm-10nm M1 = 10nm-5nm nodes= (ITRS) – see Inchon Litho public presentation] 3)450mm increasing silicon demand is needed from consortium demonstrations to support development 3)Europe momentum building - EEMI status reviewed with IRC in Potsdam [update due at Netherlands IRC meetings Apr12] 4)FI TWG extended 300mm wafer generation in parallel line item header with 450mm; 1)Including Technology upgrade assumptions through end of roadmap 2)Assuming compatibility of 300mm productivity extensions into the 450mm generation ; 5)Utilizing a new ITRS-based ICK Strategic commercial model, SEMATECH has developed 300mm and 450mm Range Scenarios for silicon and equipment demand ; ICK has updated to 2011 ITRS 12) Updated in More than Moore white paper online at 1)New Moores Law and More Graphic update included in 2011 ITRS Executive Summary 2)MtM Workshop completed in Potsdam, GE, in April and reviewed at Summer ITRS meeting 3)New MEMS TWG and Chapter added to 2011 ITRS 4)Proposals for 2013 ITRS consideration: tbd; ITRS MtM cross-TWG work; plus Weds, 4/25 Europe workshop includes new iNEMI applications driver presentation (Grace OMalley/Europe iNEMI Mgr. – highlights on Automotive; Medical; Energy; Lighting; et al) ) 2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)

5 5 Technology Pacing Cross-TWG Study Group (CTSG) work preparation for 2012 Update [move to 2013 ITRS Renewal (kickoff Dec12) including new cooperation with PIDS, M&S, and the NIST, ST (MASTAR), and Purdue (TCAD) modeling teams]: 2011 Renewal ITRS ORTC Technology Trend Summary (cont.) –IRC Equivalent Scaling Graphic Update Included in 2011 Update: Parallel bulk and SOI pathways; and Clarification of gate mobility materials pathway Proposals for pull-in placement of MuGFET [2012 Update work] [preparation for 2013 ITRS] and III/V Ge Timing [consider in 2013 ITRS work] (one IDM or Foundry company may lead technology production ramp) –PIDS and FEP Memory Survey Proposal Updates Additional acceleration will be monitored [see 2012 ITRS Update Proposals] –FEP and Design and System Drivers Logic Monitor Monitor MPU and Leading Edge Logic technology trends [2012 Proposals for 2013 ITRS] –A&P/Design Power (Thermal) Model [2012 proposals for 2013 ITRS] Possible proposals for Power Dissipation "hot spot" model rather than chip area basis –PIDS/Design Max On-chip Frequency vs Intrinsic Modeling Included in 2011 Update: New Max Chip Frequency trends (reset to 3.6Ghz/2010 plus 4% CAGR trend) TBD PIDS Intrinsic Transistor and Ring Oscillator model Changes to 8% [from unchanged % trend (supported past 8% Design Frequency trend)] PIDS Updates include MASTAR static modeling near-term and TCAD dynamic long-term modeling Also equivalent scaling tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional scaling; timing to include IRC proposal for Leading Co. driver timing –YE Defect Density Modeling New ORTC Defect Density model work moved to 2012 Update due to loss of modeling resources [2012 proposals for 2013 ITRS]

6 6 More than Moore: Diversification More Moore: Miniaturization Combining SoC and SiP: Higher Value Systems Baseline CMOS: CPU, Memory, Logic Biochips Sensors Actuators [e.g. MEMS] HV Power Analog/RFPassives 130nm 90nm 65nm 45nm 32nm 22nm 16 nm. V Information Processing Digital content System-on-chip (SoC) Beyond CMOS Interacting with people and environment Non-digital content System-in-package (SiP) Source: 2011 ITRS - Exec. Summary Fig. 4 Figure 4The Concept of Moores Law and More

7 7 More Poly Dense Lines added in 2010 ITRS Update [Note: The ITRS does not utilize any single-product node designation reference; Flash Poly and DRAM M1 half-pitch are still Lithography drivers; however, other product technology trends may be drivers on individual TWG tables] Source: 2011 ITRS - Exec. Summary Fig. 1 Metal Pitch Typical DRAM/MPU/ASIC Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Typical flash Un-contacted Poly FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/ Lines Poly Pitch Exec. Summary - Figure 1 Definition of Half-Pitch

8 Work in Progress - Do Not Publish 8 Months Alpha Tool DevelopmentProduction Beta Tool Production Tool First Conf. Papers Proposal: First 1-2 Companies Reaching Combined Production (work in Progress) K 20K 200K Additional Lead-time: ERD/ERM Research and PIDS Transfer Volume (Wafers/Month) Source: 2009 ITRS - Exec. Summary Fig. 2a Figure 2a - (within an established wafer generation*) - *see also Figure 2a for ERD/ERM Research and PIDS Transfer timing; and also - Figure 6 (450mm topic) for Typical Wafer Generation Pilot and Production Ramp Curves Production Ramp-up Model and Technology/Cycle Timing Proposal * For 2012 Update Note: Fewer leading IDM Companies Requires Adaption of Definition To allow one IDM Company Or a Foundry Representing Many Fabless Companies To Lead a Technology Production Ramp Timing *Proposal Note: Leadership company First Manu- facturing could set more aggressive first production target, since fast followers may trail 1-3 years

9 9 Months Alpha Tool Development Production Beta Tool Product Tool Volume (Wafers/Month) K 20K 200K Research Transfer to PIDS/FEP (96-72mo Leadtime) First Tech. Conf. Device Papers Up to ~12yrs Prior to Product Hi- Channel Example: 1 st 2 Cos Reach Product First Tech. Conf. Circuits Papers Up to ~ 5yrs Prior to Product Hi- Channel Proposal - for 2013 ITRS work Source: 2011 ITRS - Exec. Summary Fig. 2b; plus: Figure 2bA Typical Technology Production Ramp Curve for ERD/ERM Research and PIDS Transfer timing - including an example for III/V Hi-Mobility Channel Technology Timing Scenario - Acceleration to 2015 Scenario for the 2012 Update work [http://www.eetimes.com/electronics-news/ /Intel-s-Gargini- pushes-III-V-on-silicon-as-2015-transistor-option ]http://www.eetimes.com/electronics-news/ /Intel-s-Gargini- pushes-III-V-on-silicon-as-2015-transistor-option ITRS Near Term (2011 – 2019) ITRS Long Term (2019 – 2025)

10 Work in Progress - Do Not Publish 2009 ITWG Table Timing: nm45nm 32nm22nm 16nm 2011 IS ITRS DRAM M1 : 2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm MPU/hpASIC Node: 45nm 32nm/28 22/20nm 16/14nm 11/10nm 8/7nm 2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm 2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm 45nm32nm 22nm15nm 11nm 2011 IS ITRS Flash Poly : 54nm Source: Proposal 2011 ITRS - Executive Summary Fig tbd 450mm Production Ramp-up Model 2012 ITRS Proposal [ Modified from 2009 ITRS Figure 2c A Typical Wafer Generation Pilot Line and Production Ramp Curve ] Versus Node vs. actual contacted M1 and un-contacted Poly Half-Pitch alignment [ 7/27 Note for 450mm Special Topic: Need Consortium Development and Demonstration Update and Silicon Consumption model in light of latest Consortium plans… ] [Backup] *Note: At ITRS/USA, the IRC recommended updating the ITRS 450mm Timing Graphic for use in the 2011 ITRS Roadmap guidance; based on guidance from SEMATECH suggestions for modification and commentary in an Executive Summary Topic. Volume Years Alpha Tool Beta Tool Silicon is supporting development using partially-patterned and processed test wafers --IDM & Foundry - Pilot Lines Manufacturing Demonstrations focus on 1xnm M1 half-pitch capable tools DevelopmentProduction Increasing 450mm Silicon Demand From Demonstrations Beta Tool Production Tool < Consortium ITRS 450mm Production Ramp-up Model [Modified from 2009 Figure 2c A Typical Wafer Generation Pilot Line and Production Ramp Curve ] Demonstration nm nm nm 1x nm MPU = DRAM 2013/14 MPU < DRAM 2015 on M1: 2-yr Cycle? 2017 on M1: 2-yr Cycle? Proposal for consideration in 2012 ITRS Update work for Proposals for 2013 ITRS Kickoff Hsinchu Dec, 2012: continue to extend M1:on 2-yr Cycle through 2017/13nm (8/7nm node)?

11 11 [See Litho Inchon December Public ITRS acrobat Foil #4,5]

12 Work in Progress - Do Not Publish 12 Year of Production Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] DRAM ½ Pitch (nm) (contacted)[1,2] MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] MPU High-Performance Printed Gate Length (GLpr) (nm) [1] MPU High-Performance Physical Gate Length (GLph) (nm)[1] ASIC/Low Operating Power Printed Gate Length (nm) [1] ASIC/Low Operating Power Physical Gate Length (nm)[1] ASIC/Low Standby Power Physical Gate Length (nm)[1] MPU High-Performance Etch Ratio GLpr/GLph [1] MPU Low Operating Power Etch Ratio GLpr/GLph [1] Long-term Years Table ORTC-1 ITRS Technology Trend Targets Year of Production Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] DRAM ½ Pitch (nm) (contacted)[1,2] MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] MPU High-Performance Printed Gate Length (GLpr) (nm) [1] MPU High-Performance Physical Gate Length (GLph) (nm)[1] ASIC/Low Operating Power Printed Gate Length (nm) [1] ASIC/Low Operating Power Physical Gate Length (nm)[1] ASIC/Low Standby Power Physical Gate Length (nm)[1] MPU High-Performance Etch Ratio GLpr/GLph [1] MPU Low Operating Power Etch Ratio GLpr/GLph [1] Near-term Years 2011 ORTC Table 1 [Unchanged for 2012 Update; tbd 2013 ITRS Renewal] 450mm Production Target : ITRS EUV Intro: DRAM&Flash: 2013 MPU: 2015 MPU/hpASIC Node(nm): ITWG Table Timing: year Node Cycle /2yrs = /yr 2011 ITRS M1 2yr cyc(nm): ITRS M1 3yr cyc (nm): ??

13 ITRS Figure 11 – ORTC Table 1 Graphical Trends – Memory Half Pitch [With 2011 Flash 3D Scenario Overlay] Source: 2011 ITRS - Executive Summary Fig 3 UNCHANGED However, FOR 2012 CTSG WORK: DRAM 4f2/14; 3D Flash 2016/16 48nm – op. C ? 3D - 8 layers 3D layers PIDS 3D Flash : Looser Poly half-pitch /32; Then /28nm Then /24nm Then /18nm ~5.5-yr Cycle Long-Term nm 3D -16layers/48nm? 3D -256layers/24nm?4-yr cycle? 5.5-yr cycle

14 14 Long-Term nm 2011 ITRS Figure 4 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length Source: 2011 ITRS - Executive Summary Fig 4 UNCHANGED FOR 2012 CTSG WORK; but Proposals to be Considered

15 15 Long-Term nm 2011 ITRS Figure 4 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length Source: 2011 ITRS - Executive Summary Fig 4 Flash Trends DRAM Trends UNCHANGED FOR 2012 CTSG WORK; but Proposals to be Considered [ MPU vs. Memory ]

16 16 Long-Term nm 2011 ITRS Figure 4 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length Source: 2011 ITRS - Executive Summary Fig 4 Flash Trends DRAM Trends ? 2012 ITRS Work:22nm (ITRS 2011 Planar M1=38nm ; GL=24nm) MugFET M1=??nm; 3D Physical Gate Length = ??nm? 2-year M1 pace extension to 2017 ; then 3yrs again 2012 ITRS Work Consider: 7nm pull-in to 2017 (ITRS 2011 Planar M1=14nm); 2019 ITRS GLph = 11.7nm unchanged; except for MugFET M1=??nm; 3D and FDSOI Physical Gate Length = ??nm? Logic and Flash (3yr cycle) both drive Lithography after 2017; Logic M1 after 2022? MuG-FET FDSOI

17 2011 ITRS Figure 5 Equivalent Scaling Roadmap for Logic (MPU and high performance ASIC) Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic nodes and ITRS trends for comparison); also including proposals for MugFET and III/V Ge acceleration for 2012 ITRS Update work Metal High k Gate-stack material Bulk FDSOI Multi-gate (on bulk or SOI) Structure (electrostatic control) Channel material Metal High k 2nd generation Si + Stress S D High-µ InGaAs; Ge S D PDSOI Metal High k nth generation Possible Delay Possible Pull -in 17 68nm45nm 32nm22nm 16nm 2011 ITRS DRAM M1 : 2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm MPU/hpASIC Node: 45nm 32nm 22/20nm 16/14nm 11/10nm 8/7nm 2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm 2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm 45nm32nm11nm 2011 ITRS Flash Poly : 54nm 2011 ITWG Table Timing: Proposals - for 2013 ITRS preparation nm nm 22nm 15nm 11nm Source: 2011 ITRS - Executive Summary Fig 5 *Proposal Note: Leadership company First Manu- facturing could set more Aggressive first production target, since fast followers may trail 1-3 years With 2012 ITRS IRC Guidance Update Proposal Note*: [ PIDS/FEP/Design HP/LOP/LSTP Sub-Team Transistor Modeling Work Underway ] 450mm 1 st Production

18 Source: 2011 ITRS - Executive Summary Fig ITRS Figure 5 Equivalent Scaling Roadmap for Logic (MPU and high performance ASIC) Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic nodes and ITRS trends for comparison); also including proposals for MugFET and III/V Ge acceleration for 2012 ITRS Update work Metal High k Gate-stack material Bulk FDSOI Multi-gate (on bulk or SOI) Structure (electrostatic control) Channel material Metal High k 2nd generation Si + Stress S D High-µ InGaAs; Ge S D PDSOI Metal High k nth generation Possible Delay Possible Pull -in 18 68nm45nm 32nm22nm 16nm 2011 ITRS DRAM M1 : 2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm MPU/hpASIC Node: 45nm 32nm 22/20nm 16nm/14nm 11/10nm 8/7nm 2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm 2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm 45nm32nm11nm 2011 ITRS Flash Poly : 54nm 2011 ITWG Table Timing: Proposals - for 2013 ITRS preparation nm nm 22nm 15nm 11nm Proposal - for 2013 ITRS prep MPU = DRAM 2015 on M1 2-yr Cycle? MPU < DRAM 2017 on M1 2-yr Cycle? FDSOI MugFET pull-in to 14nm/2014? /ibm-staying-on-soi-technology-for- 14nm-finfets/ …IBM will move to finFETs based on silicon-on-insulator wafers at the 14 nm node…. …You dont need well contacts. And anyone who does a cost analysis will conclude that the cost of isolation in bulk is comparable to the cost of the SOI wafer… …IBM has developed an embedded DRAM technology on its current SOI platform, he said carrying eDRAM forward to vertical transistors will be relatively straightforward… …The Fishkill Alliance of companies, including Samsung, GlobalFoundries, Toshiba, and others, will pursue bulk finFETs at the 14nm node… MPU/hpASIC Node(nm): ITWG Table Timing: year Node Cycle /2yrs = /yr 2011 ITRS M1 2yr cyc(nm): ITRS M1 3yr cyc (nm): Multiple companies with Bulk MugFET pull-in to 14nm/2014? *Proposal Note: Leadership company First Manu- facturing could set more Aggressive first production target, since fast followers may trail 1-3 years ?? UPDATED 04/19/12 FOR Design Discussion Prep for Europe 2012 CTSG WORK And 2013 ITRS Preparation

19 19 Long-Term nm 2011 ITRS Figure 4 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length Source: 2011 ITRS - Executive Summary Fig /2010 ITRS Unchanged (except extend to new end period): 2011 ITRS: ; also includes 2012 Update Equivalent Scaling Proposals Equiv. Scaling Gate Length Trade-off Strain HK/MG MuG-FET Hi-u,(tbd) ITRS 1999 P. Gargini Equivalent Scaling Concept FDSOI PDSOI 2011 ITRS: Extend M1; & GLpr; to 2026 on 3-year Cycle GLph versus M1 in analyzing implications 1995->2015 Nodes (10) ITRS M1 hp nm ITRS GLph nm-90nm 90nm-45nm 45nm-17nm Gate Length + Equivalent Scaling = Power & Performance Half-Pitch + Design Factor Scaling [6t SRAM = 60f2; 4t Logic = 175f2] Enables Moores Law Functions/ chip Also III/V; Ge from > 2015? Proposal for 2013 ITRS Preparation Work MugFET from > 2011; Proposal for 2012 ITRS Work for 2013 ITRS prep. Updated Equivalent Scaling Proposal - for 2012 work 450mm MPU: EUV Intro ERD/ERM : What is Next? Optical interconnect? Carbon NanoTubes/Graphene?; MRAM?; Quantum Dots Memory? Half-Pitch + Design Factors Xf2 = Moores Law ? 2012 ITRS Work:22nm (ITRS 2011 Planar M1=38nm ; GL=24nm) MugFET M1=??nm; 3D Physical Gate Length = ??nm? FDSOI MugFET pull-in to 14nm/2014? UPDATED 04/19/12 FOR Design Discussion Prep for Europe 2012 CTSG WORK And 2013 ITRS Preparation MPU/hpASIC Node(nm): ITWG Table Timing: year Node Cycle /2yrs = /yr 2011 ITRS M1 2yr cyc(nm): ITRS M1 3yr cyc (nm): Multiple companies with Bulk MugFET pull-in to 14nm/2014? 2-year M1 pace extension to 2017 ; then 3yrs again ??

20 20 Long-Term ITRS: PIDS NAND Flash Multi-Layer 3D Model Plus Slower Dimensional Reduction Rate Trend Tradeoff 2011 ORTC Figure 6 Product* Function Size Trends; plus [transistor + capacitor] Source: 2011 ITRS - Executive Summary Fig 6 Updated 04/23/12 FOR 2012 CTSG WORK MPU/ASIC Alignment Design TWG Actual SRAM [60f 2 ] & Logic Gate [175f 2 ] DRAM 4f 2 Added WAS:Begin in 2011 IS: Delayed To Flash [4f 2 ] 1) 2-yr Cycle Extended to 2010; 2) 3 bits/cell added [and extended to 2026 in the 2011 ITRS]; 3) 4 bits/cell moved from 2012 [to 2021 in the 2011 ITRS] 3D - 8 layers 3D layers 3D -16layers/48nm? 3D -256layers/24nm? 4-yr cycle? 5.5-yr cycle Flash Impact of: Vs:

21 Long-Term ITRS: Figure ITRS Product Technology Trends: Memory Product Functions/Chip and Industry Average Moores Law and Chip Size Trends Source: 2011 ITRS - Executive Summary Fig 7 4Tbits Possible with PIDS NAND Flash Multi-Layer 3D Model Scenario Option 3D layers/ /32nm/3bits/cell 4Tbits =128x33Gbits 2025/18nm/3bits/cell 13Tbits =128x99Gbits DRAM 4f 2 Added WAS:Begin in 2013 IS: Delayed To

22 22 <260mm2 <140mm2 MPU = 2x/3yrs MPU = 2x/2yrs Average "Moore's Law" = 2x/2yrs Long-Term ITRS: ITRS: Unchanged, but Extend ed Transistors/chip & Chip Size Models to 2026 On 3-year Cycle MPU/hpASIC M1 Technology Cycle and MPU Transistors/chip are On 3-year Cycle after 2013 vs. Average 2-year Historical Moores Law 22nm/(38nm M1) MPU Model Generations Figure ITRS Product Technology Trends: MPU Product Functions/Chip and Industry Average Moores Law and Chip Size Trends [unchanged from 2009, except extended to 2026] Source: 2011 ITRS - Executive Summary Fig Unchanged - Must evaluate Impact of 04/23/12 Proposals FOR 2012 IRC & CTSG Consensus Work for 2013 ITRS Consideration

23 Backup for IRC and ITWG Plenary 1.(23-26) Litho Mask Count (3 Foils) 2.(27-29) 4% Design/PIDS Frequency vs. PIDS 8% 1/(CV/I) Proposal 3.(30) MOS Transistor Scaling and Scaling Calculator 4.(31) SICAS Capacity analysis update 5.(32,33) DRAM Functions/Chip 2009 ITRS vs ITRS (2 foils) 6.(34) Planar Transistor Diagram 7.(35) Interconnect with Flash M1 Diagram 8.(36) 2008 Consortium FinFET IEDM Paper Analysis 9.(37) Wikipedia Tri-Gate references 23

24 ORTC Table 5 Update: Litho TWG model for Mask Count –MPU survey-based, mask counts peak 2014/(54 masks peak) EUV expected 2015 –DRAM referenced to MPU, mask counts peak 2012/(41 masks peak) EUV expected 2013 –Flash survey-based, mask counts peak 2012/(43 masks peak) EUV expected 2013 –Sidewall image transfer technology IEDM papers should be evaluated –Table 5 also includes NEW IC Knowledge (ICK) modeled comparison targeting ITRS 2011 Litho EUV timing; but extended out through 2024 using ITRS (www.itrs.net ) assumptions –Limited YE Defect Density modeling resources requires delay of update response to 2012 ITRS Update work 24

25 25 Fig 7a - Litho 2011 Survey vs ICK 2011 ITRS-based* Model [*extended to 2024 based on ITRS ]www.itrs.net SEMATECH Survey EUV timing: MPU in 2015; DRAM & Flash in 2013 Litho Mask Count by Product Category Actual Forecast Source: 2011 ITRS - Executive Summary Fig. 7a 450mm ICK ITRS- based v2001 MPU 300mm/ 32nm Node 59-54nm M Masks

26 26 Fig. 7b - Litho 2011 Survey vs ICK 2011 ITRS-based* Model (cont.) [*extended to 2024 based on ITRS ]www.itrs.net ICK Strategic Model* *Based on ITRS editions EUV timing: MPU in 2015; DRAM & Flash EUV in 2013 Flash Charge Trap in 2012; Multi-layer 3D begins 2016 MPU Delay EUV to 2017 Litho Mask Count by Product Category Actual Forecast Source: 2011 ITRS - Executive Summary Fig. 7b 450mm ICK ITRS- based v2001 MPU 300mm/ 32nm Node 59-54nm M Masks

27 ORTC Table 4: Design TWG Model for On- Chip Frequency –Lower model starting point 2010/3.6Ghz –4% growth rate through 2026 –*Unchanged 2011 ITRS 13% PIDS target model Intrinsic Transistor Frequency Growth; –*However, proposal for 2012 ITRS 8% PIDS target model Intrinsic Transistor Growth (work preparation in 2011) 27 Table ORTC-4 Performance and Packaged Chips Trends Year of Production Chip Frequency (MHz) WAS On-chip local clock [2] Design /IS On-chip local clock [2] Ghz Table FreqTopic tbd Chip Frequency Model Trend vs.2009/2010 ITRS Frequency Source: 2011 ITRS - Executive Summary Table tbd

28 28 Fig 8a - PIDS 2009/11 ITRS CV/I Trends vs ITRS MUG-FET 4-year Pull-In and Lower Intrinsic Freq. Trend Proposals CV/I (ps) Year of Production Ramp PIDS Table 2: CV/I – ITRS Unchanged 1/(CV/I )(Ghz) Year of Production Ramp Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.; FO 1 (capacitance example.1pf); FO 4 (capacitance example.4pf) Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.; FO 1 (capacitance example.1pf); FO 4 (capacitance example.4pf) 1/(CV/I) (Ghz) ~ ~ 13% CAGR PIDS 2012 FDSOI Scenario: 15/294 – CAGR 2011 ITRS PIDS 2011 ITRS Table: 1/(CV/I) (Ghz) = 11/156 – ~ 13% CAGR 11/ 313 – 5.4% CAGR – MugFET Trend [2012 Proposal: MugFET 4-year Leading Co. pull-in] PIDS 2011 ITRS Table: CV/I) (ps) = 11/0.64 – ~ -12% CAGR 11/ – - 4.8% CAGR – MugFET Trend [2012 Proposal: MugFET 4-year Leading Co. pull-in] CV/I (ps) ~ ~ -12% CAGR PIDS 2012 FDSOI Scenario: 15/ / % CAGR Figure 8a 2012 Update Model Trend versus 2009/2011 ITRS PIDS TWG Transistor Intrinsic Frequency (1/(CV/I)) Performance Trends Source: 2011 ITRS - Executive Summary Fig. 8a

29 29 Fig. 8b - ORTC Table 4:On Chip Local Clock Frequency Trend Comparisons to PIDS vs ITRS MUG-FET 4-year Pull-In and Lower Intrinsic Freq. Trend Proposals Figure 8b Design On-Chip Frequency vs. PIDS Intrinsic Transistor and Ring Oscillator Model Frequency 2011 ITRS Source: ITRS Test TWG compilation, ca 4Q 2010; 2011 ITRS PIDS, Design TWGs 2012 Update Scenario: FDSOI at 8% CAGR ORTC Table 4: On-Chip Local Clock Frequency: 2011 Design TWG trend: at 4% CAGR 2009/11 PIDS/FEP Ring Oscillator Model 101 invertor stages With equivalent Fan-out 4 Capacitance load; Results in Frequency of ~ 1/22 x 1/(CV/I) at ~13% CAGR Design Hroom ~ 1/ /11 ITRS PIDS/FEP Intrinsic Transistor Frequency 1/(CV/I) at 13% CAGR 2007 Des TWG Actual History of Average On-Chip Ghz – 4.9Ghz ~22% CAGR On-Chip Clock Frequency: Performance Improvement tradeoffs between dimensional EOT and Gate Length with Equivalent Scaling, both process-related (ie Strain, FDSOI, MugFET, III/V Ge, etc); and also Including design-related tradeoffs: -Multi-Core Architecture -Memory Architecture -Software Power Management -etc.] 1Thz 2012 Update Scenario: MugFET : 4yr Pull-in 1/(CV/I) to 2011; then 5% CAGR 2012 Update Scenario: MugFET at 5% CAGR 2012 Update Scenario – FDSOI: Beginning 2015 at 8% CAGR Co.A Actual Co.B Actual Co.C Actual Source: 2011 ITRS - Executive Summary Fig 8b

30 Work in Progress - Do Not Publish 30 Figure 10 MOS Transistor Scaling1974 to presentFigure 11Scaling Calculator Source: 2011 ITRS - Executive Summary ORTC Fig 1, 2

31 *Note: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of 1Q11. The detailed data are available to the public online at the SIA website, and data is located at * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 1Q data for The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that range of the feature size (y-axis). Data are based upon capacity if fully utilized. 2.5-Year DRAM Cycle ; 2-year Cycle Flash and MPU Year DRAM Cycle 3-Year Cycle Feature Size (Half Pitch) ( m) Year >0.7 m m m m m m m m m m <0.06 m = 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09/11 ITRS DRAM Contacted M1 Half-Pitch Target = 2009/11 ITRS Flash Un-contacted Poly Half Pitch Target = 2009/11 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target 4-Year Cycle for Flash after 2010 Flash pull-in; MPU 3-yr cycle after yr cycle for DRAM after pull-in Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution Source: 2011 ITRS - Exec. Summary Fig. 3

32 Work in Progress – Do Not Publish! 32 Flash (NAND) Product Size Generations 2009 ITRS Renewal: PIDS Flash Size: ??? 4x/4-5yrsWAS'09 16G64G256G1T Interim Generations: ???2007 ??? 4x/4-5yrsWAS'09 32G128G512G2T 5yrs4yrs 2011 ITRS Renewal (PIDS 2010 Update Proposal): PIDS Flash Size: x/4-5yrsWAS'09 16G 64G 256G 1T 4x/4-5yrsIS'11 64G 256G 1T Interim Generations: x/4-5yrsWAS'09 32G 128G 512G 2T n/a 4x/4-5yrsIS'11 32G 128G 512G 2T 4yrs 5yrs 4yrs ??yrs Poly uncontacted half pitch = 1-year pull-in 2010/23.8nm; then 4-year cycle to 2020; then 3-year cycle; then flat at 8nm/ Product memory size: 2 years cycle for introducing 2x product; pull-ins: 1-yr for 32G, 64G, 512G, 1T, 2T; and 2-year for 128G, 256G 128Gbit chip will be available in NAND Cell Array Efficiency unchanged from 56% in ITRS 2010

33 Work in Progress – Do Not Publish! 33 DRAM Product Size Generations 2009/10 ITRS Renewal: PIDS DRAM Size: x/6yrs G16G64G WAS'09/10 4G16G64G Interim Generations: x/5-6yrs G8G32G 4x/6yrs WAS'09/10 2G8G32G 5yrs6yrs 2011 ITRS Renewal (PIDS 2010 Update Proposal): PIDS DRAM Size: x/6yrs WAS'09/10 4G 16G 64Gn/a 4x/7yrs IS'11 4G 16G 64G Interim Generations: x/6yrs WAS'09/10 2G 8G 32G 4x/6yrs IS'11 2G 8G 32G 6yrs 7yrs? DRAM M1 half pitch = 1-year pull-in; then 3-year cycle to 2026 DRAM Product Size; Keep ITRS 2009: 2G, 4G, 8G; but 16G delay 1 yr to 2017; add 64G/2025 DRAM Cell size factor: 4F2 cell will be available in Delay 2years from ITRS2009/10 DRAM Cell Array Efficiency = 59%; versus 56.1% in ITRS 2010

34 Work in Progress - Do Not Publish ITRS Definition Work – Need Clarification of the M1 Half Pitch To clarify the ORTC Table 1 relationship to Gate Length* And for consistency with Interconnect TWG Transistor M1 contacted half-pitch [and public - sometimes presented (IEDM, etc) as Transistor Pitch or Gate Pitch] ; * vs. Printed Gate Length (GLpr) (sometimes also known as CD or Critical Dimension); and finally the publically-measurable Physical Gate Length, (GLph) [Note: The ITRS does not utilize any single-product node designation reference; Flash Poly and DRAM M1 half-pitch are still litho drivers; however, other product technology trends may be drivers on individual TWG tables] Contacted M1 Half-Pitch vs. 0.5 x Transistor or Gate Pitch? 0.5 x Transistor or Gate Pitch? [>M1 h-p?] [GLpr] [GLph] ContactWidth Metal 1 Pitch [Interconnect TWG Example; Dec10 = 2x M1 Half-Pitch] Metal 1 half-pitch = 0.5 x M1 Pitch] Other ITRS MPU Model Consideration: [SRAM (6-transistor) Cell Area = 60f2 = 60 x (M1 h-p)^2] 32 nm/56.25nm h-p, um2 [= 62.0 x ^2] [IDF 2009]

35 MPU Cross-Section Dielectric Capping Layer Copper Conductor with Barrier / Nucleation Layer Pre-Metal Dielectric Tungsten Contact Plug Inter- Mediate (=M1x1) Inter- Mediate (=M1x1) Metal 1 Passivation Dielectric Etch Stop Layer ASIC Cross-Section Semi- Global (=M1x2 ) Semi- Global (=M1x2 ) Global (=IMx1.5~2µm) Global (=IMx1.5~2µm) Inter- Mediate (=M1x1) Inter- Mediate (=M1x1) Metal 1 Global (=IMx1.5~2µm) Global (=IMx1.5~2µm) 1)MPU: Revised hierarchy 2)ASIC: No drastic change, however semi-global should be kept at 2 x M1 3)Flash: The new technology driver for M Interconnect TWG - Hierarchical Cross Sections Flash Cross-Section

36 Consortium FinFET Design Factor = 42? vs. ITRS = 60 for planar SRAM x u^2 = 171.8u2; also 60 for planar SRAM x u^2 = 85.9u2 and vs. actual IDF nm/32nm 0.171u2 area; and calc. from.092u2 area IDF09: 39.78nm/22nm : Source : 3414c.HTMSource : 3414c.HTM : …announced Dec. 16 at the 2008 International Electron Devices Meeting [IEDM] in San Francisco, California… I. Researchers from the three companies [AMD, IBM, Toshiba] fabricated a highly scaled FinFET SRAM cell using HKMG. 1) It is the smallest non-planar-FET SRAM cell yet achieved: At 0.128µm², a. the integrated cell is more than 50 percent smaller than the 0.274µm² non-planar-FET cell previously reported. b. To achieve this goal, the team optimized the processes, especially for depositing and removing materials, c. including HKMG from vertical surfaces of the non- planar FinFET structure. II. The researchers also investigated the stochastic variation of FinFET properties within the highly scaled SRAM cells and simulated SRAM cell variations at an even smaller cell size. 2) They verified that FinFETs without channel doping improved transistor characteristic variability by more than 28 percent. a. In simulations of SRAM cells of 0.063µm² area, equivalent to or beyond the cell scaling for the 22nm node, b. the results confirmed that the FinFET SRAM cell is expected to offer a significant advantage in stable operation c. compared with a planar-FET SRAM cell at this generation 2008 IEDM: 110nm Pitch 55nm Half- Pitch 32 nm/55nm h-p, um2 [= 42.3 x 0.055^2] [IEDM 2008] 22 nm/38.9nm h-p, um2 [= 41.6 x 0.028^2] [Simulation ca. 2008] ITRS MPU Model : [SRAM (6-transistor) Cell Area = 60f2 = 60 x (M1 h-p)^2] vs. actual 32 nm/56.25nm h-p, um2 [= 54.0 x ^2] [ca. 2009] 4x20 = 80nm Eq.GLph= ???nm !?

37 Work in Progress - Do Not Publish 37 ^^ "Intel Reinvents Transistors Using New 3-D Structure". Intel. using-new-3-d-structure. Retrieved 5/4/2011."Intel Reinvents Transistors Using New 3-D Structure"http://newsroom.intel.com/community/intel_newsroom/blog/2011/05/04/intel-reinvents-transistors- using-new-3-d-structure. Retrieved 5/4/ ^ a b "Transistors go 3D as Intel re-invents the microchip". Ars Technica. 5 May microchip.ars. Retrieved 7 May 2011 a b"Transistors go 3D as Intel re-invents the microchip"http://arstechnica.com/business/news/2011/05/intel-re-invents-the- microchip.ars


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