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Overall Roadmap Technology Characteristics (ORTC) 2012 1 Alan Allan Winter Hsinchu Public Conference Rev 4, 12/05/12 Hsinchu Public Conference, Rev 4,

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Presentation on theme: "Overall Roadmap Technology Characteristics (ORTC) 2012 1 Alan Allan Winter Hsinchu Public Conference Rev 4, 12/05/12 Hsinchu Public Conference, Rev 4,"— Presentation transcript:

1 Overall Roadmap Technology Characteristics (ORTC) Alan Allan Winter Hsinchu Public Conference Rev 4, 12/05/12 Hsinchu Public Conference, Rev 4, 12/05/12

2 2012 ITRS WINTER PUBLIC CONFERENCE Wednesday 5 December – Ambassador Hotel, HsinChu, Taiwan Hosted by the TSIA Jointly Sponsored by ESIA, JEITA, KSIA, SIA, TSIA, and SEMATECH MORNING SESSIONS 8:00-8:45Registration and Continental Breakfast 8:45-9:00Opening Remarks & Orientation TSIA Chair and ITRS ChairmanCarlos Diaz and Paolo Gargini Regional Greetings by the International Roadmap Committee (IRC) ESIABert Huizing JEITAHidemi Ishiuchi KSIAPaolo Gargini (acting) TSIACarlos Diaz SIAAlan Allan 9:00Session 1 Greetings by Europe IRCBert Huizing 9:00-9:15Overall Roadmap Technology CharacteristicsAlan Allan 9:15-9:30More than MooreBert Huizing 9:30-10:00System Drivers and DesignAndrew Kahng 10:00-10:15MetrologyYaw Obeng 10:15-10:25Q&A 10:25-10:45Morning Break Session 2 Greetings by Japan IRCHidemi Ishiuchi 10:45-11:00Emerging Research MaterialsMike Garner 11:00-11:15Emerging Research DevicesAn Chen 11:15-11:30InterconnectPaul Zimmerman 11:30-11:45Yield EnhancementLothar Pfitzner 11:45-11:55Q&A 12:00-13:30Lunch Hsinchu Public Conference, Rev 4, 12/05/12

3 2012 ITRS WINTER PUBLIC CONFERENCE Wednesday 5 December – Ambassador Hotel, HsinChu, Taiwan Hosted by the TSIA Jointly Sponsored by ESIA, JEITA, KSIA, SIA, TSIA, and SEMATECH AFTERNOON SESSIONS Session 3 Greetings by Korea IRCPaolo Gargini (acting) 13:30-13:45Environment, Safety, and HealthSteve Moffat 13:45-14:00Test & Test EquipmentRoger Barth 14:00-14:15MEMsMichael Gaitan 14:15-14:30RF and A/MS TechnologyMichael Gaitan 14:30-14:40Q&A 14:40-15:00Afternoon Break Session 4 Greetings by Taiwan IRCCarlos Diaz 15:00-15:15Front End ProcessesMike Walden 15:15-15:30Factory IntegrationJonathan Chang 15:30-15:45Assembly and PackagingBill Bottoms 15:45-16:00Process Integration, Devices, & StructuresRich Liu 16:00-16:10Q&A Session 5 Greetings by USA IRCAlan Allan (acting) 16:10-16:25LithographyTatsuo Chijimatsu 16:25-16:40Modeling & SimulationJürgen Lorenz 16:40-16:45Q&A 16:45-17:00Open Discussion and Closing RemarksPaolo Gargini 17:00AdjournCarlos Diaz Hsinchu Public Conference, Rev 4, 12/05/12

4 20 Years Of Technology Roadmap First NTRS workshop TWGs established. First edition of NTRS 1994, Second and third NTRS editions WSC approves internationalization of NTRS- >ITRS with Europe, Japan, Korea and Taiwan participation ITWGs established 3 workshops/year (Europe, US, and Asia) 2012 ITRS underway with 17 ITWGs 4 Hsinchu Public Conference, Rev 4, 12/05/12

5 2012 ITRS Meetings Spring Meeting April Holland. Summer Meeting July 8,9. Workshop in Monterey, CA July 12. Presentations within SEMI West Winter Meeting Dec 3-5 Taiwan Dec 3,4. Workshop Dec 5 th. Public presentation 5 Hsinchu Public Conference, Rev 4, 12/05/12

6 2012 ITRS ITWGs 1.System Drivers 2.Design 3.Test & Test Equipment 4.Process Integration, Devices, & Structures 5.RF and A/MS Technologies 6.Emerging Research Devices 7.Emerging Research Materials 8.Front End Processes 9.Lithography 10.Interconnect 11.Factory Integration 12.Assembly & Packaging 13.Environment, Safety, & Health 14.Yield Enhancement 15.Metrology 16.Modeling & Simulation 17.MEMs 6 Hsinchu Public Conference, Rev 4, 12/05/12

7 Update Figure X: Production Ramp-up Model and Technology/Cycle Timing Hsinchu Public Conference, Rev 4, 12/05/12

8 Update Figure Y: A Typical Technology Production Ramp Curve for ERD/ERM Research and PIDS Transfer Timing * including an example for III/V Hi-Mobility Channel Technology Timing Scenario Hsinchu Public Conference, Rev 4, 12/05/12

9 Update (from 2011 ITRS): Equiv Scaling & Node Alignment vs. ITRS Timing Trends Hsinchu Public Conference, Rev 4, 12/05/12

10 10 Hsinchu Public Conference, Rev 4, 12/05/12

11 11 Long-Term nm 2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length Source: 2011 ITRS - Executive Summary Fig 4 Hsinchu Public Conference, Rev 4, 12/05/12

12 12 Long-Term nm 2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length Source: 2011 ITRS - Executive Summary Fig 4 12 Hsinchu Public Conference, Rev 4, 12/05/12

13 13 Hsinchu Public Conference, Rev 4, 12/05/12

14 Updated MPU/DRAM Options We will narrow options for 22nm hp in Hsinchu Public Conference, Rev 4, 12/05/12

15 Updated Flash Options This table shows the requirements for 2-D flash development. The potential introduction of 3-D flash does not drive lithography. 15 Hsinchu Public Conference, Rev 4, 12/05/12

16 Proposal Figure Z [to replace WAS: 2012 ITRS Fig Z]: A Typical Wafer Generation Pilot Line and Production Ramp Curve applied to Forecast Timing Targets of the 450 mm Wafer Generation Hsinchu Public Conference, Rev 4, 12/05/12

17 Proposal Figure Z [to replace WAS: 2012 ITRS Fig Z]: A Typical Wafer Generation Pilot Line and Production Ramp Curve applied to Forecast Timing Targets of the 450 mm Wafer Generation Hsinchu Public Conference, Rev 4, 12/05/12

18 Proposal Figure Z [to replace WAS: 2012 ITRS Fig Z]: A Typical Wafer Generation Pilot Line and Production Ramp Curve applied to Forecast Timing Targets of the 450 mm Wafer Generation Hsinchu Public Conference, Rev 4, 12/05/12

19 More than Moore: Diversification More Moore: Miniaturization Combining SoC and SiP: Higher Value Systems Baseline CMOS: CPU, Memory, Logic Biochips Sensors Actuators [e.g. MEMS] HV Power Analog/RFPassives 130nm 90nm 65nm 45nm 32nm 22nm 16 nm. V Information Processing Digital content System-on-chip (SoC) Beyond CMOS Interacting with people and environment Non-digital content System-in-package (SiP) Source: 2011 ITRS - Exec. Summary Fig. 4 Figure 4The Concept of Moores Law and More 19 Hsinchu Public Conference, Rev 4, 12/05/12

20 More than Moore: Diversification More Moore: Miniaturization Combining SoC and SiP: Higher Value Systems Baseline CMOS: CPU, Memory, Logic Biochips Sensors Actuators [e.g. MEMS] HV Power Analog/RFPassives 130nm 90nm 65nm 45nm 32nm 22nm 16 nm. V Information Processing Digital content System-on-chip (SoC) Beyond CMOS Interacting with people and environment Non-digital content System-in-package (SiP) Source: 2011 ITRS - Exec. Summary Fig. 4 Figure 4The Concept of Moores Law and More 20 Hsinchu Public Conference, Rev 4, 12/05/12

21 1)Unchanged for 2012: MPU contacted M1 1)2-year cycle trend through 2013 [27nm (14nm node)]; then 3-year trend to )60f 2 SRAM 6t cell Design Factor 3)175f 2 Logic Gate 4t Design Factor 4)Proposal Consideration for 2013 ITRS: Extension of 2-year M1 Trend 2)Unchanged for 2012 Tables: MPU Functions/Chip and Chip Size Models 1)Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and cell design factors 2)ORTC line item OverHead (OH) area model, includes non-active area 3)Proposal Consideration for 2013 ITRS: Extension of 2-year M1 Trend 3)Unchanged for 2012 Tables: MPU GLpr, GLph – trends smoothed by 2011 PIDS modeling* 4) Unchanged for 2012 Tables: Max Chip Frequency trends (reset in 2011 to 3.6Ghz/2010 plus 4% CAGR trend) 5)Unchanged for 2012 Tables: Vdd High Performance, Low operating and standby line items from 2011 PIDS model track smoothed gate length changes* *Note: See PIDS tables for 2012 Update to be released at end of 2012 for impact due to acceleration of MugFET and FDSOI Equivalent Scaling timing into Update ITRS ORTC Technology Trend Summary 21 Hsinchu Public Conference, Rev 4, 12/05/12

22 6)Unchanged for 2012 Tables: DRAM contacted M1: 1)One-year M1 acceleration 2)New for 2012: 4f2 one-year delay to 2014 (affects Chip Size Model*) 7) Unchanged for 2012 Tables: Flash Un-contacted Poly: 1)2+-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs) trend to 2020/10nm; then 3-year trend to 2022/8nm; then Flat Poly after 2022/8nm 2)and 3bits/cell extended to 2018; 4bits/cell delay to )Unchanged for 2012 Tables: DRAM Bits/Chip; Chip Size Model adjusted*: 1)3-year generation Moores Law bits/chip doubling cycle target (1-2yr delay for smaller chip sizes <30mm2 – 2x/2.5yrs) 2)*Chip Size Model adjusted for 4f2 one-year delay to )Unchanged for 2012 Tables: Flash Bits/Chip and Chip Size Model: 1)3-year generation Moores Law bits/chip doubling cycle target (after 1-yr acceleration; then 1-2Tbits; keep chip size <160mm2) 2)3D on-chip bit layers with relaxed half-pitch tradeoffs are included for maximum bits per chip 1)New 2012 Update Survey Emphasis: layer range from 8/32nm -128/18nm Layers to 16/48nm – 256/24nm Layers (option C in 2011 ORTC Table 2) 2012 Update ITRS ORTC Technology Trend Summary (cont.) 22 Hsinchu Public Conference, Rev 4, 12/05/12

23 10) Unchanged for 2012 Tables: ORTC Table 5 - Litho # of Mask Counts MPU, DRAM, 1)Litho Survey inputs Unchanged for )IC Knowledge (ICK) model contribution extends mask levels range to )2013 Update: update ICK model to 2011 Mask Counts 11) Updated for 2012 Update [and 2013 ITRS Preparation]: IRC 450mm Timing Graphic Position: 1)Timing Status Updated for 2012 and 2013 ITRS guidance 1)Consortia work continues 2)IDM and Foundry Pilot lines: ; 3)Risk Start Production: [corrected early target in 2012 Update; move to 2016 in 2013 ITRS Targets] 2)G450C Consortium continues good progress on 450mm program activities to meet the ITRS Timing 1)Consortium operations are using 450mm early test wafer process, metrology and patterning capability to support Supplier development 2)193 immersion multiple exposure litho tools are under development to support consortium and manufacturers schedules for target 1xnm technology goal 3)450mm increasing silicon demand is needed from consortium demonstrations to support development 3)Europe Position Unchanged – EEMI450 status was reviewed with IRC in Netherlands Apr12 4)300mm wafer generation in parallel line item header with 450mm; 1)Including Technology upgrade assumptions 2)Assuming compatibility of 300mm productivity extensions into the 450mm generation; 5)ITRS-based ICK Strategic Model commercially available and updated to 2011 ITRS, including 300mm and 450mm Range Scenarios for silicon and equipment demand 12) Unchanged for 2012 Update: More than Moore white paper online at 1)MtM Workshop completed in Netherlands, in April and reviewed at Summer ITRS meeting 1)Europe workshop included new iNEMI applications presentation (by Europe iNEMI Mgr. – highlights on Automotive; Medical; Energy; Lighting; et al) 2)ITRS MEMS TWG and Chapter cross-roadmap work underway for 2013 iNEMI Roadmap 2012 Update ITRS ORTC Technology Trend Summary (cont.) 23 Hsinchu Public Conference, Rev 4, 12/05/12

24 Technology Pacing Cross-TWG Study Group (CTSG) 2012 work preparation for 2013 ITRS Renewal (kickoff Dec12), including: 2013 Renewal Preparation ITRS ORTC Technology Trend Summary (cont.) 24 –IRC Equivalent Scaling Graphic Update Updated timing placement of MuGFET, FDSOI, and III/V Ge Timing; now based on one IDM or Foundry company, who may lead technology production ramp –Design and FEP Logic Technology Trends Monitor and Update MPU and Leading Edge Logic technology trends, including Ongoing- evaluate alignment of nodes with latest M1 industry status Consider High Performance vs. Low Power transistor type needs Consider extending 2yr cycle to at least 2017/14nm (7nm node) Functions/Chip and Chip Size Models tbd; based on final consensus of new proposals On-Chip Frequency Proposals – Align with PIDS modeling and evaluate/update to industry trends –PIDS and FEP Memory Survey Proposal Updates Presently unchanged for 2013 – ongoing monitor of DRAM and Flash technology trends –Litho and FEP (and PIDS and Design) Survey for CD Variability and Control Monitor and Update Litho and Etch Gpr/Gph Ratio for CD control trends –A&P/Design Power (Thermal) Model Develop proposals for Power Dissipation "hot spot" model rather than chip area basis –PIDS/Design Max On-chip Frequency vs Intrinsic Modeling Targeted for 8% (vs. 13%) CAGR (1/CV/I) intrinsic transistor performance (to align with 2011 ITRS 4% Design Frequency trend) Consider Intrinsic Transistor and Ring Oscillator model Changes Including MASTAR static modeling near-term and Purdue dynamic long-term modeling Including equivalent scaling tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional scaling –YE Defect Density Modeling Update ORTC Defect Density model work to latest Litho Mask Count Model – still seeking defect modeling resources support Hsinchu Public Conference, Rev 4, 12/05/12

25 Summary The Technology Roadmap turns 20! ITRS is a live and evolving process, mapping semiconductor industry needs and challenges ahead of implementation The initial NTRS 11 chapters have became 17 The ITRS is used as a reference document by the whole semiconductor industry Public presentations: July 12, 2012 during SEMICON West; and December 5, 2012 in Hsinchu Taiwan Publicly accessible on line at 25 Hsinchu Public Conference, Rev 4, 12/05/12

26 Public Conference Backup Industry Historical Gate Density and SRAM Cell Size Trends 2012 ITRS Gate Density and SRAM Cell Size analysis Work in Progress Transistor Dimensional Definitions… 26 Hsinchu Public Conference, Rev 2, 11/28/12

27 27 Long-Term ITRS: ORTC Figure 6 Product Function Size Trends [transistor + capacitor] Source: 2011 ITRS - Executive Summary Fig 6 MPU/ASIC ITRS 2011 Target 6-transistor 22nm Node SRAM [60f 2 ] = um2 cell 37.84nm M1 half-pitch 0.18u x 0.48u = um2 ITRS MPU/ASIC Alignment Design TWG Actual SRAM [60f 2 ] & Logic Gate [175f 2 ] MPU/ASIC ITRS 2011 Target 6-transistor 32nm Node SRAM [60f 2 ] = 0.172um2 cell 53.51nm M1 half-pitch 0.25u x 0.68u = 0.172um2 MPU/ASIC Historical 1997 Target 6-transistor SRAM [60f 2 ] = 10um2 cell 428nm M1 half-pitch Intel 6T Pentium Pro L2 cache = 33um2 …0.35u minimum gate… UMC 2Mbit/11.25; Samsung 4Mbit/11.7; Winbond 4T1Mbit SRAM = 10.15um2 …using the samie technology generation (0.3um process)… …analyzed by ICEs laboratory in 1996… [Source: IC Insights 1997 Fig. 8-12: cd/MEMORY97/SEC08.PDF ] 0.3um 0.35um minimum gate 22 nm/39.8nm h-p, um2 [= 58.0 x ^2] [IDF 2009] 32 nm/56.25nm h-p, um2 [= 54.0 x ^2] [IDF 2009] < f2 M1 cycle 0.5x/2yrs = -29% CAGR [4 plus Resistor Load] Hsinchu Public Conference, Rev 4, 12/05/12

28 < x/2yrs = 41% CAGR > x/3yrs = 26% CAGR Near Term Long Term ITRS Flash Poly H-pitch ITRS DRAM M1 H-pitch Logic Node: ITRS M1 H-pitch [2013 Proposal]: Gate Density 2011 and 2012 ITRS: Unchanged 2-year cycle through 2013 Hsinchu Public Conference, Rev 4, 12/05/12

29 ITRS : < x/7yrs ~ 2x/2yrs = 41% CAGR Gate Density Historical Perspective IC Insights Historical Data: on ~2-year cycle 29 Hsinchu Public Conference, Rev 4, 12/05/12

30 < x/2yrs = -29% CAGR > x/3yrs = -21% CAGR Near Term Long Term SRAM Cell Size 2011 and 2012 ITRS: Unchanged 2-year cycle through ITRS Flash Poly H-pitch ITRS DRAM M1 H-pitch Logic Node: ITRS M1 H-pitch [2013 Proposal]: Hsinchu Public Conference, Rev 4, 12/05/12

31 31 SRAM Cell Size Scaling Transistor density continues to double every 2 years 45 nm, um 2 (193 nm dry) 32 nm, um 2 (193 nm immersion) 65 nm, um 2 (193 nm dry) < f2 M1 cycle 0.5x/2yrs = -29% CAGR SRAM Historical Perspective (Data: on ~2-year cycle) [Source: VLSIR weSRCH Website] Hsinchu Public Conference, Rev 4, 12/05/12

32 32 Transistor Density and Performance Drive currents continue to increase while gate pitch scales Gate Pitch (nm) 0.7x every 2 years 32nm 65nm 45nm nm Pitch Gate Pitch (nm) Drive Current (mA/um) V, 100 nA I OFF 45nm 32nm 65nm 90nm NMOS PMOS 130nm Transistor and M1 Pitch Perspective vs. Drive Current/Performance (Data: on ~2-year cycle) [Source: VLSIR weSRCH Website] Hsinchu Public Conference, Rev 4, 12/05/12

33 ITRS Definition Work – Clarification of the M1 Half Pitch To clarify the ORTC Table 1 relationship to Gate Length* And for consistency with Interconnect TWG Transistor M1 contacted half-pitch [and public - sometimes presented (IEDM, etc) as Transistor Pitch or Gate Pitch] ; * vs. Printed Gate Length (GLpr) (sometimes compared to CD or Critical Dimension for manufacturing process control); and finally the publically-measurable Physical Gate Length, (GLph – see also the PIDS chapter) [Note: The ITRS does not utilize any single-product node designation reference; Flash Poly and DRAM M1 half-pitch are still litho drivers; however, other product technology trends may be drivers on individual TWG tables] GLph Hsinchu Public Conference, Rev 4, 12/05/12

34 2011 Interconnect TWG - Hierarchical Cross Sections 34 Hsinchu Public Conference, Rev 4, 12/05/12


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