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DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference 2004 ITRS Update ORTC Overview Nodes, Chip Size, Transistors, Capacity, $ Trends Alan.

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Presentation on theme: "DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference 2004 ITRS Update ORTC Overview Nodes, Chip Size, Transistors, Capacity, $ Trends Alan."— Presentation transcript:

1 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference 2004 ITRS Update ORTC Overview Nodes, Chip Size, Transistors, Capacity, $ Trends Alan Allan/Intel Corp 7/14/04 2004 ITRS Interim Status Review [Presentation Rev Version 5b]

2 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference 2004 (2004 ITRS Exec. Summary and ORTC) – its all about: Economics + Technology…and Customers, who Buy Products (emulated and mapped to chips) which, though the customers dont know or appreciate it, need Semiconductor : Nodes Chip Sizes Transistors Capacity $

3 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference 90s21st Century Semiconductor Industry Technology Economics Semiconductor Industry Clear Both Economics + Technology Hurdles = Growth

4 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Wanted: CUSTOMERS, who breathe, eat, and live in….. Materials Semiconductor Equipment Semiconductors Electronic End Equipment Sources: NASA.gov ; SEMI Customer Demand Global & Regional Political & Macro-Economic Environments Ecosystem or Foodchain? …and who BUY, based on varying levels of Purchasing Power, PRODUCTS Semiconductor Equipment & Materials

5 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Products (As Defined by NEMI PEGs*) * Product [Need] Emulator Groups

6 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Drivers MPUDSP AMS Memory Network Portable Office SIP/SOC (ITRS) Applications (NEMI) Chips /Fabrics (ITRS) Medical AutomotiveDefense Architectures A1A1 A2A2 A3A3 A4A4 Figure 1: Potential mapping approach between NEMI and ITRS roadmaps Source: ITRS Design TWG SIP/SOC

7 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Nodes

8 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Production Ramp-up Model and Technology Node Volume (Parts/Month) 1K 10K 100K Months 0 -24 1M 10M 100M Alpha Tool 1224 -12 DevelopmentProduction Beta Tool Production Tool First Conf. Papers First Two Companies Reaching Production Volume (Wafers/Month) 2 20 200 2K 20K 200K Source: 2003 ITRS - Exec. Summary Fig 2 Fig 2

9 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Source: 2003 ITRS - Exec. Summary Table C hp22hp32hp45hp65hp90 2018 2016 2015 2013 2012 2010 2009 2007 2006 2004 2003 2002 [Actual] Year of Production hp130 Technology Node [DRAM] (nm) Technology Nodes: Back to 3-year cycle 3-Year Technology Cycle 2-Year Technology Cycle [1998-2002actual] Near TermLong Term

10 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Source: STRJ, ITRS PIDS ITWG Survey, ca. 2Q03 3-year Node-Cycle 2-year Node-Cycle 3-year Node-Cycle 2020 ITRS 2003: 2003/100(-110nm?) - 2019/16nm: Average 0.5x/2.5years Company A Company B Company C [DRAM Half-Pitch] [DRAM] 0304

11 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference 2003 ITRS Renewal ORTC Table Header/Targets: 2003 ITRS Technology Node Header (**Unchanged from 2001/2002 ITRS): Near-Term Long Term Notes ---------------------------------- -------------------------------- ----- 2003 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018 hp90 hp65 hp45 hp32 hp22 DRAM Unchanged 100 90 80 70 65 57* 50* 45 35* 32 25* 22 18* Other ORTC Tracked Technology Trends (optional - use by TWG Tables as needed): Poly Unchanged 107 90 80 70 65 57* 50* 45 35* 32 25* 22 18* NEW Logic M1: 120 107 95 85 76 67 60 54 48 42 38 34 30 27 24 21 UNCHANGED: MPU Pr GL: 65 53 45 40 35 32* 28* 25 22 20* 18 16 15* 13 11 10* MPU Ph GL: 45 37 32 28 25 22* 20* 18 16 14* 13 11 10* 9 8 7* * Not visible in 2001 ITRS due to no annual columns between "Near Term" and "Long Term" column ranges. The 2001 ITRS Long Term columns are retained for continuity of technology nodes. ** DRAM Half-Pitch Nodes unchanged, however cell design factor improvement has been significantly delayed in the 2003 ITRS. Node timing is based on original 2001 ITRS glossary definition of 10Ku/mo manufacturing with Production-Capable Equipment and Materials. *** Note: Logic Half-Pitch (HP) was based on Un-contacted Logic Poly HP in 2001 ITRS. In the 2003 ITRS, Logic Metal 1 (M1) was added and correlated with IC TWG Local Wiring Pitch/2 [120nm/2003, plus a 3-year target cycle trend]. ** ***

12 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Chip Sizes

13 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference

14 572mm2 Litho Field Size 286mm2 2 per Field Size 800mm2 Litho Field Size MPU Chip size (mm2) – Historical Trends vs Unchanged 2001-03 ITRS Model* 1000 100 10 198019851990199520002005201020152020 CP MPU 140mm2 HP MPU 310mm2 CP Shrink 70mm2 * ITRS Design TWG MPU Transistors/Chip Model: ~2x/Node = 2x/2yrs from 1999 - 2001; then 2x/3yrs from 2001- 2016 *1999 Leading- Edge.18u CP MPU: 512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2 *1999 Leading- Edge.18u HP MPU: 2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x 5.19u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2 New: 704mm2 Litho Field Size

15 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Transistors

16 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Transistors – VLSI Research May03 [source: tci030509graphicsSPCL2.xls] [Transistors] [1971-2003 (1e3)^(1/16yrs) = 54% Ave CAGR]

17 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference 19491952195519581961196419671946 …In the beginning… Bell Labs ca. 1947 Transistors – VLSI Research May03 [source: tci030509graphicsSPCL2.xls] 20032006200920122015201820212000 Exa-Transistors (Et) 1e18 Tera-Transistors (Tt) 1e12 Mega-Transistors (Mt) 1e06 Giga-Transistors (Gt) 1e09 Peta-Transistors (Pt) 1e15 Zeta-Xistors (1e21) One-a-Transistor (t) 1e00 Kilo-Transistors (Kt) 1e03 Moores Law @ 2x/1yr Integrated Circuit (IC) … TI & Fairchild ca. 1959 Moores Law @ 2x/1.5-2yrs ITRS -- Near Term Moores Law @ 2x/2yrs ITRS -- Long Term Moores Law @ 2x/3yrs [Transistors] 50Pt You are Here! Semico (SIA): 1997 Product Units (B) Discrete 197.00 Analog 25.90 Other Memory 3.90 Other Logic 14.80 SubTotal: 241.60 MCU 4.20 MPR 1.80 DRAM 3.30 Flash 0.57 MPU 0.26 Total: 251.73 Est. from Semico: 1997 Product Transistors (Pt) Discrete 0.0002 Analog 0.130 Other Memory 0.98 Other Logic 1.78 SubTotal: 2.88 MCU 0.84 MPR 0.36 DRAM 42.9 Flash 1.71 MPU 0.78 Total: 49.47 [1971-2019 (1e3)^(1/16yrs) = 54% Ave CAGR]

18 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Capacity

19 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Technology Node Compared to Actual Wafer Production Capacity Technology Node Distribution Fig 3 Feature Size (Half Pitch) ( m) Year 199719981999200020012002200320062005 Feature Size of Technology 0.01 0.1 1 10 W.P.C >0.7 m 0.7-0.4 m 0.4-0.3 m 0.3- 0.2 m <0.16 m 0.2- 0.16 m Source: SICAS** W.P.C.= Total Worldwide Wafer Production Capacity (Relative Value *) W.P.C * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2003. The area of each of the production capacity bars corresponds to the relative share of the Total MOS IC production start silicon area for that range of the feature size (y-axis). Data is based upon capacity if fully utilized. <0.4 m <0.3 m <0.2 m <0.16 m 20042007 ITRS Technology Node 25%25% 25 % ** Source: Semiconductor Industry Capacity Statistics (SICAS) – collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2003 Source: 2003 ITRS - Exec. Summary Fig 3 hp350 Actual hp90hp65 hp250 Actual hp180 Actual hp130 Actual 3-Yr 2-Yr SIA/SICAS Data: 1-yr delay from ITRS Timing to 25% of MOS IC Capacity 25 %? hp127nm hp180nm hp255nm hp360nm hp510nm hp720nm hp90nm <0.11um Fcast

20 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference ISMT/IEM [Semico] IC Product Technology Profile 140nm 180nm 255nm 360nm 650 nm 690 nm 820 nm 225 nm 770 nm 910 nm 127nm 90 nm 65 nm 45 nm 290 nm 400 nm 560 nm 460 nm * SICAS Most Leading Edge Node Range** = 25-30% of MOS IC Area, Actual ** Examples: 180nm = 0.22u-0.18u-0.15u; 130nm = 0.15u-0.13u-0.11u; 90nm = 107nm-90nm-75nm SICAS Node* >25% of MOS IC Capacity 2003 ITRS hpXX (Actual); PrGl ; PhGL Leading Edge Mfg Roadmap Node 1994199519961997199819992000200120022003 1.00 0.40 0.10 0.20 OIC: EPROM; Mass Storage; Gate Arrays; Voice and Other; EEPROM; Std Logic; Analog / Linear LEM: DRAM Flash LEL: MPU DSP OLE: Graphics ; Std Cell; PLD; MROM; Chipsets; SRAM; Comm; MCU LEM, LEL L.Edge Average All Leading Edge Average Other IC Average 04

21 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference $, Gestalt

22 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference World Electronics, Semi, Tools, Si Area, #Fabs, Wafer Units vs. GWP ($B) 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 195819601962196419661968197019721974 1976 19781980198219841986198819901992199419961998200020022004 2006 Bilion Dollars ($B); Silicon Sq.In. (Msi/1e4); #Wafers (w / NPW) (Mu/1e4) Tool Sales ($B)Chip Sales ($B)Electronics Sales ($B) GWP ($B)Silicon Sq. Inches (Msi/1e4) Silicon Wafers (Mu/1e4) Total # Fabs (20Kwspm - #/1e04) Source: VLSIR, April, Sept 2001 History <-2000 -> F'cast 0-1%? 8.26% 29% 47% 4.2% 2.8% 47% 1% 10% 7.5% 6-8%? 7.5-10%? 15.5 % 5-8%? Macro Overview – GWP, Revenue, Capacity Demand Snapshot As of 10/23/02 USA GDP AVE ~3-4% 2010 2020 $ $ $ $ 10% CAGR? 1 Tera-Dollar 00 WAS:

23 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference [VLSIR ca May03] [~7.5% CAGR] [~15.5% CAGR] Past < -- 2002 02 WAS:

24 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Past Future VLSIR History: CAGR 90-00 = 6.8% CAGR 90-01 = 5.6% Estimate: CAGR 02-08 = 5.8% 10% CAGR 7% -7.5%CAGR

25 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference $

26 What Can History Teach Us? Portability & Connectivity Wave Multiple Wireless Devices Fuel Cells, Rich Media Source: Semico Research Corp, May04 Internet Wave Internet Boom, Cell Phones Digital Content Personal Computing Analog Wave TV, VCR 2020 $1T $0.5T 5 th Wave? 6 th Wave? 7 th Wave? Growing to $1T will require a few more Waves of emerging Applications, Economies, and Customers! (and, yes, a couple more wafer generations or equivalent productivity improvements!) 7.5% 10% 3 / 4 5 / 6 200mm300mm450mm675mm You Are Here! Total Semi 2003: $166B Source SIA/WSTS Total Semi Revenue Digital Wave

27 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Summary ITRS Node timing [DRAM Half-Pitch based] is based on the first two leading-edge companies beginning manufacturing ramp ITRS Nodes [DRAM Half-Pitch based] are forecast to slow from the present 2-year to a 3-year pace after 2003, and slowing design factors are causing density to double only every technology node Leading-edge DRAM Product first production start Chip Sizes are targeted to remain flat at about 140mm2 for affordability, but will shrink further in size To keep chip sizes affordable [ie flat], the ITRS target Moores Law DRAM functionality per chip is slowing from 2x/1.5-2yrs to 2x/2.5-3yrs Leading-edge volume Capacity Demand, as monitored by SICAS, is on the same 2-year pace as the ITRS nodes, with the 130nm technology range ( 110nm) reaching >25% of MOS IC capacity in 2003

28 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Summary (cont.) There appears to be no slowing in the overall demand for transistors, which has averaged over 50% compound growth since the 70s – a pace which increases demand 1000 times every 16 years To keep the cost per transistor and per bit affordable to end-use applications and consumers, the cost to manufacture transistors inside finished semiconductor devices must decrease at a -29% compound rate The ITRS targets the affordable cost per function reduction target is based on a historical target of -29%, and if this cost reduction can be maintained as demand for total transistors grows at a 53-55% rate, the revenue of the industry could grow at 7.5-10% per year, reaching $1T by 2019-2025 from the 1999 level of $145B Of course, growing to $1T will require more emerging Waves of demand and a couple more wafer generations or equivalent productivity improvements!

29 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference 2003/2004 ITRS Technology Node Trends Figure 7 2003 ITRSHalf Pitch Trends [2004 Update – Unchanged]

30 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference 2003/2004 ITRS Technology Node Trends Figure 8 2003 ITRSGate Length Trends [2004 Update – Unchanged]

31 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Table 1a Product Generations and Chip Size Model Technology NodesNear-term Years Year of Production2003200420052006200720082009 Technology Nodehp90hp65 DRAM ½ Pitch (nm)100908070655750 MPU/ASIC Metal 1 (M1) ½ Pitch (nm)1201079585766760 MPU/ASIC ½ Pitch (nm) (Un-contacted Poly)107908070655750 MPU Printed Gate Length (nm) 65534540353228 MPU Physical Gate Length (nm)45373228252220 ASIC/Low Operating Power Printed Gate Length (nm) 90756553454035 ASIC/Low Operating Power Physical Gate Length (nm)65534537322825 [2004 Update – Unchanged]

32 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference Table 1b Product Generations and Chip Size Model Technology NodesLong-term Years Year of Production201020122013201520162018 Technology Nodehp45hp32hp22 DRAM ½ Pitch (nm)453532252218 MPU/ASIC Metal 1 (M1) ½ Pitch (nm)544238302721 MPU/ASIC ½ Pitch (nm) (Un-contacted Poly)453532252218 MPU Printed Gate Length (nm) 252018141310 MPU Physical Gate Length (nm)1814131097 ASIC/Low Operating Power Printed Gate Length (nm) 322522181613 ASIC/Low Operating Power Physical Gate Length (nm) 22181613119 [2004 Update – Unchanged]

33 DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Public Conference ISMT IEM Wafer Generations Sc. C - ITRS 2001 (3/2/3 year) 300mm 530 wo 450mm 360 370 730 133mm 540 wo 200mm 370 835 89mm 540 wo 133mm 770 200mm 430 wo 300mm 340 745 430 200mm @20Kwspm = 32Bcm2 200 133mm @20Kwspm = 6.7Bcm2 =89 equiv 200mm fabs 540 133mm @20Kwspm = 18Bcm2 540 89mm @20Kwspm = 8Bcm2 530 300mm @20Kwspm = 90Bcm2 160 133mm @20Kwspm = 12Bcm2 =71 equiv 300mm fabs Lead-Time to Evaluate Potential Solutions: ~7yrs ahead of 2011-12 Source: International SEMATECH Industry Economic Model (IEM) Version 3 ca 2001; High Scenario; VLSI Research, Inc. xxx = # 20Kwspm Fabs without next Wafer Generations


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