Presentation on theme: "DeHon 2008 1 Devils Advocate View: CMOL, FPNI, nanoPLA…. André DeHon Benjamin Gojman, Nikil Mehta During the canonization process."— Presentation transcript:
DeHon Devils Advocate View: CMOL, FPNI, nanoPLA…. André DeHon Benjamin Gojman, Nikil Mehta During the canonization process of the Roman Catholic Church, the Promoter of the Faith (Latin Promotor Fidei), popularly known as the Devil's Advocate (Latin advocatus diaboli), was a canon lawyer appointed by the Church to argue against the canonization of the candidate. It was his job to take a skeptical view of the candidate's character, to look for holes in the evidence, to argue that any miracles attributed to the candidate were fraudulent, etc. -- WikipediacanonizationRoman Catholic ChurchLatincanon lawyerskepticalmiracles
DeHon Case Molecules are not miraculous. Miracle of high density is exaggerated. Miracle of low energy is a slight of hand. Curse of variation falls on all who would dare reach the atomic-scale.
DeHon Two Ideas Benefits follow from two hypotheses: 1.Can fabricate parallel wires denser than arbitrary topology 2.Can place resistance-varying switch with quasi-non-volatile state in space of dense wire crossing Hysteretic switching No extra area to program Valid Prospects? Lets build regular architectures around resistive switches!
DeHon Inquisition What problem does CMOL/FPNI solve? Is this the bottleneck to scaling?
DeHon Problem Solved? What problem do these technology hypotheses address? –Density –(Economical) density ASIC Mgates/cm ITRS 2007 Execsum Table 1i; assume 4TR/gate 11
DeHon Unpack Assumptions Previous table appears to assume –100,000 F 2 per gate in FPGA case 250,000 F 2 / 4-LUT × 2.5 gates/4-LUT Plausible, conservative –64 F CMOS 2 per gate in CMOL case assuming each buffer is a gate and buffer is 64F 2 –This assumption is stated in FPGA2006 paper. –Optimistically small. …plausibly within factor of 2. Ignores that most of these buffers will act as route through (provide no gates).
DeHon Right Problem? Is logic density of gates the bottleneck in scaling? –Economical logic density? –Density of programmable gates?
DeHon What is the Scaling Bottleneck? Density? Delay? Power Density? Reliability? Test and handling economics?
DeHon Methodology: Benchmark-Level Quantification For following, map Toronto 20 benchmarks –20 Largest MCNC benchmarks –Order of 10K gates each (so think small cores) Composite density/performance/energy –Includes overheads, route-through, fanout…
DeHon Density: Mapped Logic Strukov and Likharev FPGA2006 Only about 1 in 4 gates used as logic –775/4 190 comparable to ASIC gate density
DeHon How much density from nanowires? Look at F cmos =F nano =22nm (F cmos /F nano largest) –42 Mgates/cm 2 20× better than CMOS FPGA 5--20× worse than Fnano=3nm F CMOS (nm) F nano (nm) (Mgates/cm 2 ) Conservative Extreme CMOS FPGA CMOL revised CMOS ASIC
DeHon Delay Challenge has been to turn capacity (area) into performance –Linear scaling considered excellent Something which is 10× denser –Better be less than 10× slower E.g. we expect 10 cores running at 100MHz to run slower than 1 core running at 1GHz If give up too much delay, no benefit.
DeHon Obtaining Performance Highly Pipelined nanoPLA designs –Conservative (demonstrated tech.) R onxpoint =100K Si = cm, NiSi = cm Only NiSi non-active areas Likharev only claim about 1GHz (unpipelined). (Nanoarch2007) F CMOS (nm) F nano (nm) Delay (ns) Conservative Extreme CMOS FPGA CMOL revised CMOS ASIC Pipe delay stages = 452
DeHon What-If Extensions F CMOS (nm) F nano (nm) Conservative (ns) Defect Free(ns) Perfect Restore(ns) Defect Free Perfect Restore(ns) Copper 2 CMOS Buf. No Litho (ns) Extreme (ns)
DeHon Power Density Clock rates stopped scaling due to power density We can already fabricate more transistors than we can afford to activate. –Looking at gate capacitance alone (45nm) (highly optimistic, no wire) 6× J/Tr/op (V dd =1V) ×700MTr/cm 2 ×10GHz = 420W/cm 2 (3000W/cm 2 at 22nm, V dd =0.7V)
DeHon Power Density: Quantitative F CMOS (nm) F nano (nm) Conservative (ns) (Mgates/cm 2 ) Vdd=0.7V (W/cm 2 ) Extreme (ns) (Mgates/cm 2 ) Vdd=0.7V (W/cm 2 ) Vdd=0.3V (W/cm 2 ) What if we run them at full speed? CMOL dodge here is assuming Vdd=0.3V.
DeHon Power Density: Quantitative What can we use at 100W/cm 2 ? F CMOS (nm) F nano (nm) (ns) (Mgates/cm 2 ) V (W/cm 2 ) V (W/cm2)100 Extreme Factor (Mgates/cm2) (ns)
DeHon Energy per Gate Evaluation (CMOL) Fcmos Fnano Cwire (fF) Egate(0.3v) fJ Egate(0.3v)/kTln(2) / ,00060,000 kTln(2) per gate at T=300K Cg,total (FO4)0.18fF 22nm CMOS W=2F cmos Vdd= ,000 kTln(2) for T=300K Vdd=0.3 2,800 kTln(2)
DeHon Reliability: Can we lower the voltage? Lower voltage + Lower energy/op –Less headroom for V t variation More leakage, lower performance More bad parts compensate with sparing ? Subthreshold Operation Trade energy for performance –Fewer electrons defining state Higher susceptibility to transient upset –Thermal, shot ionizing particles.
DeHon Upset Rates Lower Voltage to achieve 100W/cm 2 –Assume (10% activity) –V=176mV (1GHz, 22nm,3Ggates/cm 2 ) 1cm 2 FIT Rates –Thermal [calc. based on Kish PhysLetA 2002] –Shot [calc. based on Kish FNL2004] Increase in upset rate V=700mV to 176mV –Ionizing Particle upsets increase × [calc. based on Cohen IEDM1999, Degalahal ISQED2004] –Lack information for absolute grounding. Suggestions for better sources for reliability calculations appreciated.
DeHon Variation and Yield Are voltages plausible given variation? ASIC: optimistic bound –Require devices have 00 and V th (1+k )
DeHon Testing and Handling Highly defective nanoPLA/CMOL/FPNI exploit component- specific mapping to tolerate Demands painful paradigm shift Assume can run mapping in 4 hrs on 250W workstation –1KWhr/chip x $0.15/1KWhr = $0.15 –(2000 Wafers/day x 675 dies/wafer) / 6 = 225,000 Workstations »But those live at customer site… not to mention handling …. Penn IC Group have ideas to address.
DeHon Bottleneck Conclusion Work in an E-D-A-Relability trade space Density is not the clear limiter Big hope is to trade this density to address other problems –Power density –Energy –Variation –Reliability
DeHon Additional Assumptions By Style CMOL –Pins above metallization FPNI –Nanoscale alignment of lithographic contacts Not just parallel lines Kuekes says litho rotated (7/12) nanoPLA –Relatively reliable assembly of large number of NWs –Reasonably controlled production of doped (coded) NWs
DeHon Inquisition Report If believed could achieve roadmap –CMOS ASICs provide higher performance If need fine-grained programmability –Variation –Economics force few unique platforms …benefit from inexpensive programmability – × density benefit –Plausible performance (as far as energy allows) Maybe 1GHz instead of 10GHz (1/10 th the speed) –Reduce energy through sparing/repair to contain variation Will cost post-fabrication handling
DeHon Summing Up Molecules are not miraculous. Miracle of high density is exaggerated. –Non-existent compared to ASIC –Closer to 2 orders of magnitude than 3 for FPGA Miracle of low energy is a slight of hand. –Comes with a curse on reliability. Curse of variation falls on all who would dare reach the atomic-scale. –…grace of repair may be all that saves us –Not unique to CMOL Small switches may help.
DeHon References nanoPLA articles Likharev, Hybrid CMOS/Nanoelectronic Circuits(CMOL, FPNI, etc.), White Paper for ITRS ERD Working Group 2008 Strukov and Likharev, FPGA 2006 Likharev and Strukov, Nanoarch 2007
DeHon Langmuir-Blodgett (LB) transfer Can transfer tight-packed, aligned SiNWs onto surface –Maybe grow sacrificial outer radius, close pack, and etch away to control spacing + Transfer aligned NWs to patterned substrate Transfer second layer at right angle Whang, Nano Letters 2003 v7n3p951