1. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 1 - DAAD An Educational Electronic Prototype System for Phase-Locked Loop Based Circuits Eltimir Stoimenov (1), Ivаilo Pandiev (2) e_stoimenov@tu-sofia.bg (1), ipandiev@tu-sofia.bg (2) Technical University of Sofia

2. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 2 - DAAD Our objective: To develop a laboratory stand which helps students to understand the basics of the PLL circuits. Why? Because PLL circuits are widely applied in communication, electronics and computer sciences. In this order students should possess a high level of knowledge in the PLL theory.

3. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 3 - DAAD What we have done: We have designed a versatile educational PLL stand which incorporates the most important applications of the PLL circuits: - phase locking; - frequency synthesis with integer and non-integer coefficients; non-integer coefficients; - frequency demodulation.

4. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 4 - DAAD FREQUENCY DIVIDER 1 0 - 512 FREQUENCY DIVIDER 2 0 - 512 PCVCO COMPIN SIGIN VCOIN VCOOUT R1 R2 C1AC1B P C1OUTP C2OUTP C3OUTP CPOUT PLL 4046 R1R2 C1 R3 R4 C2 LPF_2 INOUT IN OUT LPF_1 OUTPUT DEM_OUT FM generator INPUT FM generator: Allows frequency demodulation - Central frequency: 0-1MHz; - Adjustable deviation; - Adjustable data signal frequency. -Data signal PWM output - Based on MSP430F5310 PLL circuit: -Based on 4046 IC - Students can set the VCO parameters by external components Frequency dividers: Allows frequency synthesis - Programmable coefficients -9bits resolution -Based on MSP430G2553 Low Pass Filter: - Lag-lead type (one pole, one zero); -Allows the students to set the capture range PWM_OUT

5. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 5 - DAAD Experimental results 1. Frequency synthesis FREQUENCY DIVIDER 1 0 - 512 FREQUENCY DIVIDER 2 0 - 512 COMPIN SIGIN VCOIN VCOOUT P COUT PLL 4046 LPF_2 IN OUT IN OUT LPF_1 OUTPUT DEM_OUT FM generator INPUT PWM_OUT 2. Frequency demodulation LPF_3 - PWM output

6. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 6 - DAAD Laboratory stand part -1Laboratory stand part -2

7. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 7 - DAAD Exercise set, part 1: 1. Study the Phase-Loop-Locked circuit realized with 4046 IC. Consider the following input parameters: - VCO central frequency – f O = 100 kHz for V VCOIN = 1/2V CC ; - Lock range - 2f L = 100 kHz; - Settling time – tset = 1 ms for maximum ripples ≤ 5% ; - Overshoot ≤ 20% and settle to within 5% at w n t = 5. 2.Calculate all the external VCO components – R1, R2 and C1. Calculate the values of the LPF_1 components - R3, R4 and C2. For the calculation use the nomograms and formulas given 4046 datasheet from Philips. 3. Set the components values according the calculation you made in the previous point. Apply a square wave signal of 5 V magnitude and frequency of 100 kHz. The frequency dividers and the FM generator should not be connected to the circuit. - Measure the VCO controle voltage – VCOIN; - Use an oscilloscope to observe the input and the output signals. Measure the frequencies of the signals; - Determine the width of the lock range. Find the f MIN and f MAX frequencies and measure the corresponding VCO control voltages. Compare the values with the input parameters.

8. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 8 - DAAD Exercise set, part 2: 4. Synthesize output signals with frequencies of 90 kHz to 110 kHz with step of 1 kHz. In this order connect the two frequency dividers to the PLL circuit and change the division coefficients appropriately. Apply a square wave input signal of 5V magnitude and frequency of 1 kHz. The FM generator should not be connected to the circuit. 5. Realize a frequency demodulator using the PLL circuit. For this purpose connect the FM generator to the input and by using the rotary encoder adjust the signal as follows: carrier signal central frequency: 100 kHz; deviation: ±40%; data signal frequency: 100 Hz. Connect the VCOIN signal to LPF_2 input and observe the demodulated signal in the LPF_2 point. The original data signal is also PWM modulated and after filtering it can be observed in PWM_OUT point. Compare the two signals. The frequency dividers should not be connected to the circuit.

9. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 9 - DAAD The pilot test of the developed educational prototype system will be performed in 2012 with hundred of 3rd year regular students within 24 learning hours. In particular the educational system is a part of the laboratory practice of the Mixed- signal system course. The evaluation of the system will be focused on usability of the learning material, instructional effectiveness and learners’ attitudes. The chosen block structure provides possibilities for future extension of the developed system with additional elements and functionality. THE PILOT TEST

10. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 10 - DAAD CONCLUSIONS The developers’ team achieved the following results of the of the : - Development of a procedure for PLL circuits study; - Development of an educational electronic prototype system based on monolithic PLL 4046. The created system allows to study some of the basic PLL circuit applications, such as phase locking process, frequency synthesis and frequency demodulation; - Creating students’ guide and assignments for supporting the created educational prototype system.

11. Projekt „ESSNBS“ Niš, November 4 th – 7 th, 2012 - 11 - DAAD Thank you for your attention For more information please contact us on: e_stoimenov@tu-sofia.bg