Presentation on theme: "ITRS - YE ITWG Conference in HsinChu December 5, 2012 Lothar Pfitzner"— Presentation transcript:
1 ITRS - YE ITWG Conference in HsinChu December 5, 2012 Lothar Pfitzner
2 Scope of Yield Enhancement AspectsManufacturing of integrated semiconductor devices: numerous processing steps building the 3D structure of the chip (e.g. 9 Cu and low –k interconnect layers for 32 nm)Yield: percentage of operating chips at the end of the manufacturing processComponentsDetermination and control of contaminationInspection of structures and critical dimensionsModel to predict and calculate yield based on historic contamination levels (particulate and metals) and defects (failures)Determination of kill ratios: Correlation between defects and yieldA bird’s-eye view of 0.128µm2 FinFET SRAM cells (post silicide formation)Toschiba,45 nm ramp production was the fastestPresented by Mark Bohr (Intel) 02/2009Gordon Moore: “There is no fundamental obstacle to achieving device yields of 100%.” (Electronics, 38 (8), 1965)
3 Example: Inspection for ‘More than Moore’ Applications‘More Moore’and‘More than Moore’ technologiespower electronicsmechatronicsMEMS applicationspackaging and assembly3 D integrationLaboratory scale inspection setup fulfilling requirements of low cost components and large area inspection (4 mm *4 mm field of view at µm resolution) (example for 3D integration, EC & BMBF funded project JEMSIP3D under contract ENIAC Call 2008 / )Test layout routing lines (CEA Leti)
4 Contamination Analysis for Manufacturing Control Driversultra clean manufacturingunintended contamination of layersdimensional, structural and compositional informationdepth resolved quantificationnon-volatile organic surface contaminationAnalytical Techniques for Manufacturing Controlx-ray metrologyGCMSTBDHEPA Filter for contamination free manufacturing (source wikipedia)For metals, Grazing Incidence X-Ray Fluorescence (GIXRF) could be a possible solution providing dimensional quantification and qualification of surface near elemental contamination.Elemental depth profiling with GIXRFElemental analysis of contamination with TXRF
5 Objectives of Yield Enhancement collect defect datatools for inspection and root cause analysisautomated defect classification and filteringinspection strategyyield managementsoftwareobjective: to correlate data and find excursionspredict yielddefect data excursionsdefine specsprocedure for clarificationprocessmodule 1processmodule 2processmodule kk21waferwaferwafermanufacturingdefectdensitiesinspection and collection of datadefectclassificationreview, characterization, metrology
6 Defects and Failure Mechanisms processes: litho, etch thin film implantation, planarization, cleaning,…faults and problems: defects as e.g. particles, flatness, layer properties, patterns, dimensionschallengesyield and defect map in 2 Droot cause analysis requires 3 Drequires fast and non-destructive inspection (defect density) and metrology (root cause analysis) for 2D and 3D structures CIArequires preventive defect and contamination control WECCmodel, predict and forecast yieldESD DamageInterconnectsoverlaycrackMetal 2ViaparticleopenshortMetal 1particlelayer thicknessp+nn+ppCOPn-wellp-wellcontaminationinterfaces: roughness, state density, chargesSi crystal: stacking faults, contamination, stress, COP (crystal originating particles), epi defects
7 Organization of the Chapter 2012 Chair: Lothar Pfitzner (Fraunhofer IISB) Co-Chair: Dilip Patel (ISMI)Difficult ChallengesTable YE 2Technology Requirements and Potential SolutionsWafer Environment Contamination Control (WECC)Chair: Kevin Pate (Intel) – USA, Andreas Neuber (AMAT) - EuropeTable YE 3, YE 4, YE 4aCharacterization, Inspection & Analysis (CIA)Co-Chair: H. Nagaishi and I. Thurner – EuropeTable, YE 5, YE 6, YE 7Yield Learning (YL – not active in 2012)Chair: N.N.; Contributor defined by AMATYield Model and Defect Budget (YMDB – not active in 2011 and 2012)Chair: N.N.
9 2013 Key Challenges Near Term (2013-2018) The Yield Enhancement community is challenged by the following topics:Near Term ( )Detection and Identification of Small Yield Limiting Defects from Nuisance - It is a challenge to detect multiple killer defects and to differentiate them simultaneously at high capture rates, low cost of ownership and high throughput. Furthermore, it is a dare to identify yield relevant defects under a vast amount of nuisance and false defects.Process Stability vs. Absolute Contamination Level – This includes the correlation to yield test structures, methods and data that are needed for correlating defects caused by wafer environment and handling to yield. This requires determination of control limits for gases, chemicals, air, precursors, ultrapure water and substrate surface cleanliness.Detection of organic contamination on surfaces – The detection and speciation of nonvolatile organics on surfaces is currently not possible in the fab. There is no laboratory scale instrumentation available.
10 2013 Key ChallengesThe Yield Enhancement community is challenged by the following topics:Long Term ( )Next Generation Inspection - As bright field detection in the far-field loses its ability to discriminate defects of interest, it has become necessary to explore new alternative technologies that can meet inspection requirements beyond 13 nm node. Several techniques should be given consideration as potential candidates for inspection: high speed scanning probe microscopy, near-field scanning optical microscopy, interferometry, scanning capacitance microscopy and e-beam. This assessment should include each technique’s ultimate resolution, throughput and potential interactions with samples (contamination, or degree of mechanical damage) as key success criteria.In - line Defect Characterization and Analysis – Based on the need to work on smaller defect sizes and feature characterization, alternatives to optical systems and Energy Dispersive X-ray Spectroscopy systems are required for high throughput in-line characterization and analysis for defects smaller than feature sizes. The data volume to be analyzed is drastically increasing, therefore demanding for new methods for data interpretation and to ensure quality.Next generation lithography - Manufacturing faces several choices of lithography technologies in the long term, which all pose different challenges with regard to yield enhancement, defect and contamination control.
11 Overall YE activities Activities performed since Summer Meeting: Review and update of tablesSummary text for Executive Overview 2012 revision of the YE ITRS roadmap chapter completed by September 2012(Details concerning revisions are presented by the following slides)Future Fab International Article “Yield Enhancement”Update of membership list
12 WECC: Liquid Chemicals/ Ultra Pure Water/ Gases/Precursors Recent activities:Review and update of Table YE 3 “Technology Requirements for WECC”Review and update of Figure YE 3 “Potential Solutions for WECC”Ongoing/ planned activities:Continue and expand FMEA for metals, anions, and organicsImprove particle deposition modelsUpdate CVD/ALD precursor tables
13 WECC: AMC Recent activities: Ongoing/ planned activities: Introduction of two new tables in the latest ITRS roadmap version:Table YE 4 “AMC monitoring methods”Table YE 4a “Supporting table for on-line methods”Review and text update of WECC and AMC chapterYE 3 clarification on refractory limits and footnote explanations introducedOngoing/ planned activities:Definition/standardization of „organics“Review for „AMC Definition“Introduction of EUV related contaminationDiscussion to add bare wafer suppliers requirementsReview of „Potential solutions”Adjustments of the AMC limitsIntroduction of moisture as new chemical contamination for description of reticle environmentIdentification of critical steps for moisture control in FOUP environmentReview requirements for 450 mm manufacturing
14 CIA – Activities and Messages Recent activities:Revision of tables: No changes inYE4 (now YE5) “Defect Inspection on Pattern Wafer Technology Requirements”,YE5 (now YE6) “Defect Inspection on Unpatterned Wafers: Macro and Bevel Inspection Technology Requirements”YE6 (now YE 7) “Defect Review and Automated Defects Classification Technology Requirements”.Ongoing/ planned activities:Building upon the basis of the previous „Defect Detection and Characterization“ chapter, the current scope of the chapter was defined in 2011 and confirmed during the meetings of 2010/2011/2012 as facing the characterization, inspection and analysis demands in broad applications (e.g. in the area of ‘More Moore’ and ‘More than Moore’ technologies, power electronics, mechatronics, MEMS applications, packaging and assembly):A further extension of the scope towards a better balance of defect/contamination detection and fault diagnostics/ control of electrical characteristics is under discussion. Respective ideas were first discussed during the summer meeting 2012. Proposal of Japan concerning extension of CIA focusPreparation of tables and potential solutions for the revision in 2013 needs further input of demands and intensified discussions w.r.t. their required contents.Include a new table on metal and organic contamination on wafer surfaces, bevel and edge, and backside.Include in potential solutions issues of small area detection of organics and metal contamination on wafer surfaces.Restructure of YE to be proposed by and discussed with the Japanese.
15 Proposal of Japan concerning extension of CIA focus What to do?Establish a better balance of defect/contamination detection and fault diagnostics/ control of electrical characteristics in CIA focusInclude statistical/ systematic approach into YE activitiesInclude device/ chip/ system level tables and requirements into ITRS2013 YE chapterWhy?Extra/ Missing materials are root cause of yield excursion Physical inspection often requires intensive efforts Such faults are more easily approached by detection of abnormal device behaviour/ chip malfunction manifesting itself in out-of-spec electrical parameters
16 Proposed example of classification for CIA methodologies Current focus of CIA chapter:physical defect detection on wafer (including particle/ contamination)Shrink of devices lack of accordant measurement capacityObjective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation
17 Proposed example of classification for CIA methodologies Acquisition of electrical characteristics of devices in general faster than acquisition of values of the physical layerObjective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation
18 Proposed example of classification for CIA methodologies Characteristics of chip layer: Pass/ FailShort test time for one pattern (compared to measurement of electrical characteristics), Fault diagnosis recognizes device defectObjective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation
19 Proposed example of classification for CIA methodologies Allows investigation of possible dependencies between data and prediction of yield or electrical characteristicsObjective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation
20 Outlook Development/ Improvement of the Yield Enhancement chapter Discussion of the focus of YE chapterWhat are the pros and cons of referring to not only physical/process defects but also to device defects and abnormal electrical characteristics of a device?Does a change of emphasis in YE (CIA) activities make sense (e.g. with respect to the advent of MtM, inclusion of back end Yield, 450 mm technology)?What about including an improved combination of yield of products/fault diagnosis/control of electrical characteristics and defect/contamination detection of the wafer with the respective statistics in YE activities in order to achieve reasonable yield enhancement?Should we include tables for virtual metrology and for advanced control strategies?Reflection of current status and future requirements needs subsequent adjustment of outline and content of the chapterKeep tables for Front End Processing updatedAdd Back End Yield Enhancement specificationsLook into Assembly and Packaging yield enhancementDetermine the requirements w.r.t. yield enhancement for manufacturing ofMore MooreMore than Moore3DLarger diameter substratesMasks