Presentation on theme: "Conference in San Francisco"— Presentation transcript:
1Conference in San Francisco ITRS - YE ITWGConference in San FranciscoJuly 12, 2012Lothar Pfitzner
2Scope of Yield Enhancement AspectsManufacturing of integrated semiconductor devices: numerous processing steps building the 3D structure of the chip (e.g. 9 Cu and low –k interconnect layers for 32 nm)Yield: percentage of operating chips at the end of the manufacturing processComponentsDetermination and control of contaminationInspection of structures and critical dimensionsModel to predict and calculate yield based on historic contamination levels (particulate and metals) and defects (failures)Determination of kill ratios: Correlation between defects and yieldA bird’s-eye view of 0.128µm2 FinFET SRAM cells (post silicide formation)Toschiba,45 nm ramp production was the fastestPresented by Mark Bohr (Intel) 02/2009Gordon Moore: “There is no fundamental obstacle to achieving device yields of 100%.” (Electronics, 38 (8), 1965)
3Example: Inspection for ‘More than Moore’ Applications‘More Moore’and‘More than Moore’ technologiespower electronicsmechatronicsMEMS applicationspackaging and assembly3 D integrationLaboratory scale inspection setup fulfilling requirements of low cost components and large area inspection (4 mm *4 mm field of view at µm resolution) (example for 3D integration, EC & BMBF funded project JEMSIP3D under contract ENIAC Call 2008 / )Test layout routing lines (CEA Leti)
4Contamination Analysis for Manufacturing Control Driversultra clean manufacturingunintended contamination of layersdimensional, structural and compositional informationdepth resolved quantificationnon-volatile organic surface contaminationAnalytical Techniques for Manufacturing Controlx-ray metrologyGCMSTBDHEPA Filter for contamination free manufacturing (source wikipedia)For metals, Grazing Incidence X-Ray Fluorescence (GIXRF) could be a possible solution providing dimensional quantification and qualification of surface near elemental contamination.Elemental depth profiling with GIXRFElemental analysis of contamination with TXRF
5Objectives of Yield Enhancement collect defect datatools for inspection and root cause analysisautomated defect classification and filteringinspection strategyyield managementsoftwareobjective: to correlate data and find excursionspredict yielddefect data excursionsdefine specsprocedure for clarificationprocessmodule 1processmodule 2processmodule kk21waferwaferwafermanufacturingdefectdensitiesinspection and collection of datadefectclassificationreview, characterization, metrology
6Defects and Failure Mechanisms processes: litho, etch thin film implantation, planarization, cleaning,…faults and problems: defects as e.g. particles, flatness, layer properties, patterns, dimensionschallengesyield and defect map in 2 Droot cause analysis requires 3 Dmodel, predict, and forecast yield YM&DBrequires fast and non-destructive inspection (defect density) and metrology (root cause analysis) for 2D and 3D structures DDCrequires preventive defect and contamination control WECCESD DamageInterconnectsoverlaycrackMetal 2ViaparticleopenshortMetal 1particlelayer thicknessp+nn+ppCOPn-wellp-wellcontaminationinterfaces: roughness, state density, chargesSi crystal: stacking faults, contamination, stress, COP (crystal originating particles), epi defects(YM&DB: defect budget and yield modelling DDC:
7Organization of the Chapter 2011 Chair: Lothar Pfitzner (Fraunhofer IISB) Co-Chair: Dilip Patel (ISMI)Difficult ChallengesTable YE 2Technology Requirements and Potential SolutionsWafer Environment Contamination Control (WECC)Chair: Kevin Pate (Intel) – USA, Andreas Neuber (AMAT) - EuropeTable YE 3Characterization, Inspection & Analysis (CIA)Chair: A. Nutsch and I. Thurner – EuropeTable YE 4, YE 5, YE 6Yield Learning (YL – not active in 2012)Chair: N.N.; Contributor defined by AMATYield Model and Defect Budget (YMDB – not active in 2011 and 2012)Chair: N.N.
92012 Key Challenges Near Term (2012-2018) The Yield Enhancement community is challenged by the following topics:Near Term ( )Detection and identification of Small Yield Limiting Defects from Nuisance - It is a challenge to detect multiple killer defects and to differentiate them simultaneously at high capture rates, low cost of ownership and high throughput. Furthermore, it is a dare to identify yield relevant defects under a vast amount of nuisance and false defects.Process Stability vs. Absolute Contamination Level – This includes the correlation to yield test structures, methods and data are needed for correlating defects caused by wafer environment and handling. This requires determination of control limits for gases, chemicals, air, precursors, ultrapure water and substrate surface cleanliness.Detection of organic contamination on surfaces – The detection and speciation of nonvolatile organics on surfaces is currently not possible in the fab. There is no laboratory scale instrumentation available.
102012 Key ChallengesThe Yield Enhancement community is challenged by the following topics:Long Term ( )Next Generation Inspection - As bright field detection in the far-field loses its ability to discriminate defects of interest, it has become necessary to explore new alternative technologies that can meet inspection requirements beyond 13 nm node. Several techniques should be given consideration as potential candidates for inspection: high speed scanning probe microscopy, near-field scanning optical microscopy, interferometry, scanning capacitance microscopy and e-beam. This pathfinding exercise needs to assess each technique’s ultimate resolution, throughput and potential interactions with samples (contamination, or degree of mechanical damage) as key success criteria.In - line Defect Characterization and Analysis – Based on the need to work on smaller defect sizes and feature characterization, alternatives to optical systems and Energy Dispersive X-ray Spectroscopy systems are required for high throughput in-line characterization and analysis for defects smaller than feature sizes. The data volume to be analyzed is drastically increasing, therefore demanding for new methods for data interpretation and to ensure quality.Next generation lithography - Manufacturing faces several choices of lithography technologies in the long term, which all pose different challenges with regard to yield enhancement, defect and contamination control.
11WECC: UPW ActivitySelective defect density in the critical areas requires better understandingIons/Metals – still critical – no change in the roadmapParticles:On-line metrology for particles in liquid does not address killer particle size and therefore filtration efficiency for killer particles is not completely knownElectrically active particles are considered more critical than electrically non-active particlesNGL technologies requires stricter particles’ control, e.g. EUV mask cleaning and nano-imprintWorking with SEMI on developing a standard for the filter performance validationOrganicsWorking on new definition of critical organics, based on FEP input (non-volatile)Using FMEA for better definition of critical organics in future
12WECC: AMC activitiesNew AMC Monitoring table ; relevant analytical proceduresin acc. to YE3 table- Online vs. off-line analytical methods- Method limitation and detection limits- New! FOUP environment samplingOngoing activities:- Definition/standardization of „organics“- Review for „AMC Definition“- Introduction of EUV related contaminationDiscussion to add bare wafer suppliers requirementsReview of „Potential solutions „Adjustments of the AMC limitsIntroduction of moisture as new chemical contamination for descriptionof reticle environment- Identification of critical steps for moisture control in FOUP environment
13CIA - MessagesCIA builds upon the basis of the previous ‘Defect Detection and Characterization’ chapter.The scope was defined in 2011 facing the demands in broad applications, e.g. in the area of ‘More Moore’ and ‘More than Moore’ technologies. Also power electronics, mechatronics and MEMS applications, furthermore, characterization, inspection and analysis demands and requirements from packaging and assembly have been taken into account. This major change of the scope was decided in the meetings of 2010/2011/2012.In addition, an extension of the scope towards a better balance of defect/contamination detection and fault diagnostics/ control of electrical characteristics is under discussionTables and potential solutions will be prepared for the revision in 2013.
14Cross Cut Activity 2011 (Yield - Assembly) Goal: Implementation of Assembly requirements in the YE RoadmapApproach: initial surveyResponsible: Ines Thurner (CONVANIT), Klaus Pressel (IFX)
15Summary Spring 2011 Defect Budget Survey: Organisation: WECC (new): two contributors from Europe identified in 2010no Asian and US contribution subTWG suspended, see belowOrganisation:the subchapters YL and DB&YM were suspended as a consequence of missing support from Asia & US & IDM Consequently, YE was not to be able to supply Electrical Defect Densities for ORCT tables!the subchapter Defect Detection & Characterisation (DDC) was changed to Characterization, Inspection & Analysis (CIA)Scope:supply tool specifications for leading edge defect density characterization & More than Mooredefine requirements in the future for wafer contamination analysis on the surface, at interfaces and in the bulkContributors: IDM, Suppliers, WECC, P&A, MEMSWECC (new):separation of reticle environment and wafer environmentseparation of FOUP, RSP (Reticle SMIF Pod) and ambient environment improvement / clarification of table YE7 proposed by Japan TWGCTWG MeetingInclude YE in back-endLeading edge vs. MtM vs. mainstream technology
16Discussion of the Focus of YE What are the pros and cons of referring to not only physical/process defects but also to device defects and abnormal electrical characteristics of a device?Does a change of emphasis in YE (CIA) activities make sense (e.g. with respect to the advent of MtM, Inclusion of back end Yield, 450 mm technology)?What about including an improved combination of yield of products/ fault diagnosis/ control of electrical characteristics and defect/contamination detection of the wafer with the respective statistics in YE activities in order to achieve reasonable yield enhancement?
17Proposals of Japan concerning extension of CIA focus What to do?Establish a better balance of defect/contamination detection and fault diagnostics/ control of electrical characteristics in CIA focusInclude statistical/ systematic approach into YE activitiesInclude device/ chip/ system level tables and requirements into ITRS2013 YE chapterWhy?Extra/ Missing materials are root cause of yield excursionPhysical inspection often requires intensive efforts Such faults are more easily approached by detection of abnormal device behaviour/ chip malfunction manifesting itself in out-of-spec electrical parameters
18Proposed example of classification for CIA methodologies Current focus of CIA chapter:physical defect detection on wafer (including particle/ contamination)Shrink of devices lack of accordant measurement capacityObjective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation
19Proposed example of classification for CIA methodologies Acquisition of electrical characteristics of devices in general faster than acquisition of values of the physical layerObjective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation
20Proposed example of classification for CIA methodologies Characteristics of chip layer: Pass/ FailShort test time for one pattern (compared to measurement of electrical characteristics), Fault diagnosis recognizes device defectObjective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation
21Proposed example of classification for CIA methodologies Allows investigation of possible dependencies between data and prediction of yield or electrical characteristicsObjective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation
22Outlook Development/ Improvement of the Yield Enhancement chapter Reflection of current status and future requirements needs subsequent adjustment of outline and content of the chapterKeep tables for Front End Processing updatedAdd Back End Yield Enhancement specificationsLook into Assembly and Packaging yield enhancementDetermine the requirements w.r.t. yield enhancement for manufacturing ofMore MooreMore than MooreLarger diameter substratesMasks