2 Test ITWG Membership Industry Suppliers * New in 2001 Agere Hitachi IBMInfineonIntelMatsushitaMotorolaPhilipsST Microelectronics*Texas InstrumentsSuppliersAdvantestAgilentInovys*SchlumbergerSynopsys*Teradyne* New in 2001
3 2001 ITRS Test Chapter New Additions Updates Reliability Methods Material HandlingDevice Interface TechnologyUpdatesHigh Frequency Serial CommunicationsHigh Performance ASICHigh Performance MicroprocessorLow-end MicrocontrollerMixed Signal and WirelessDFT TesterEmbedded and Commodity DRAM and Flash
4 2001 Key Challenges High Speed Device Interfaces Highly Integrated Designs & SOCsReliability ScreensManufacturing Test Cost ReductionTest Software StandardsModeling and Simulation
5 Demand for BandwidthPenetration of high speed interfaces into new designs is increasing dramaticallyLearning rate for ATE solutions lags leading edge device technologyTest and DFT methods must be developed to enable development and production test of these products
6 High Integration Devices & SOC Customer requirements for form factor and power consumption are driving a significant increase in design integration levelsTest complexity will increase dramatically with the combination of different classes of circuits on single die or within a single packageDisciplined, structured DFT is a requirement to reduce test complexityNew test methods and equipment architectures must be developedEnable a merge of logic and analog test capability with the throughput of high density memory test equipment
7 Reliability Screens Run Out of Gas Critical need for development of new techniques for acceleration of latent defectsBurn-in methods limited by thermal runawayLowered use voltages limits voltage stress opportunityDifficulty of determining Iddq signal versus “normal” leakage current noiseNew materialsRate of introduction increasing: Cu, low k, high k, SiGeIncreasing mechanical sensitivitiesRapid growth of Fabless business modelOrganizational and corporate boundaries - lack of clear ownership of reliability in distributed business models
8 Scaling Component Test Cost Recent steps have enabled test cost to begin to scale across technology nodesEquipment reuse across nodesIncreasing test throughputChallenge remains in most segments, especially high speed and high integration products
9 Dismantling the Red Brick Walls Design For Test enabling has begun to remove many of the roadblocks that appeared in the 1997 and 1999 roadmapsTest is becoming integrated with the design processImprovements demonstrated in capability and costContinued research is needed into new and existing digital logic fault models toward identification of true process defectsDevelopment of Analog DFT methods must advanceFormalization of analog techniques and development of fault models
10 Test Software Standards Focus Standards for test equipment interface & communication are needed to decrease equipment factory integration timeImprove equipment interoperability to reduce factory systems integration timee.g, built into 300mm equipment specificationsStandards for ATE software and test program generation are needed to decrease test development effort and improve time to marketLower the barrier for selecting the optimal equipmentIncreased focus for standards development and adoption of existing standards
11 Can DFT mitigate analog test cost as does in the digital domain? How can we improve manageability of the divergence between validation and manufacturing equipment?Can ATE instruments catch up and keep up with high speed serial performance trends?Can DFT mitigate analog test cost as does in the digital domain?What is the cost and capability optimal SOC test approach?What happens when high speed serial interfaces become buses?How can we make test of complex SOC designs more cost effective?Will market dynamics justify development of next generation functional test capabilities?Can DFT and BIST mitigate the mixed signal tester capability treadmill? What other opportunities exist?Will increasing test data volume lead to increased focus on Logic BIST architectures? What are the other solutions?
12 Test Implications of IP Design Test Strategy and IntegrationDFT for IP Core Based DesignHigher Level DFTStandardizationIP Core Based DesignLogicMCUMemoryControlDSPAnalogBISR/BIRAPath DelayBOSTTest StrategyAnalog IsolationScan+ATPGIP Core IsolationBIST
13 Automated DFT Insertion Automation of test control integration and test schedulingInsert test wrapper and test control circuitsSoCDFTIP CoreTest DataChip-LevelTest WrapperTestControllerInsertionConversionConfiguration of Chip-Level Test Controllerand Test Access Mechanism
14 Preliminary Roadmap for Handlers Memory2001200220032004200520062007201020132016NoteParallel Testingper head32 to 6464 to 128Index TimeSec.3 to 52 to 52 to 4Throughputthousands/ hour6 to 88 to 108 to 12Temp. Controldegree-55 to 100Temp. Accuracydegree+/- 3+/- 2+/- 2+/- 1.5*1Foot Printratio1 to 1.31.3 to 1.5*2Logic2001200220032004200520062007201020132016NoteParallel Testingper head4816Index TimeSec.0.3 to 0.4to 0.25Throughputthousands/ hour4 to 68 to 129 to1412 to 20Temp. ControldegreeRoom Temp. to 125Temp. Accuracydegree+/- 3+/- 2+/- 2+/- 1*1Foot Printratio11.21.4*2*1 Though 128 become number of parallel testing after 2005 years, it is difficult to keep the temperature accuracy that 64 are the same as the number of parallel testing with memoryhandler.Therefore, it becomes yellow. Though 8 become number of parallel testing after 2004 years, it is difficult to keep the temperature accuracy that 4 are the same as the numberof parallel testing with logic handler. Therefore, it becomes yellow.*2 It is expressed by the index number when 32 of parallel testing in 2001 is made 1. (Therefore, it becomes 1.3 by 64 of parallel testing in 2001.).
15 Preliminary Roadmap for Handlers Device flowTray flowTrayLoaderUnLoaderJEDECTemp. controlAchieving the same temperature accuracy in handlers with 128 deviceshandled in parallel, as handlers with 64 will be very difficult and challenging.Parallel testingMemory 64 to 128 (2005)Foot printConsidering the size of the handler needed to access the test floor,the test floor layout, and other transportation restrictions,the handler width should not exceed 1.8 m.Logic to 8 (2004) to 16 (2010)Make the handling faster.Make the conveyance distance shorter.More accurate positioning will makethe handling time shorter.Test headThe test head size is becoming larger year by year.SocketDeviceHandler is required to handlediversifying various kinds of packages.Index timeTest frequencyKeep an electrical stable contact
16 Preliminary Roadmap for Sockets Electrical stable contact is one of key technologieson semiconductor device testing.Important contact technologies: Probing contact for wafer testing Discussed in 2001 Socket contact for package testing Proposal for 2002 discussion
17 Preliminary Roadmap for Sockets Molded board type2001200220032004200520062007201020132016InductancenH3 to 82 to 8Contact strokemm0.3 to 0.5Contact pressureg20 to 4020 to 40Contact resistancemOhm30Guarantee marginal valuedurability10000NoteThe performance has ripened and there is no big change. Contact pressure is difficult at lead free correspondence.Spring probe type2001200220032004200520062007201020132016InductancenH2 to 81 to 8Contact strokemm0.3 to 0.50.3Contact pressureg20 to 4013 to 4013 to 28Contact resistancemOhm150100Guarantee marginal valuedurability100001000010000NoteThe limit over the diameter reduction of a terminal is in sight.New generation type2001200220032004200520062007201020132016InductancenH1 to 8Contact strokemm0.1 to 0.3Contact pressureg13 to 28Contact resistancemOhm30Guarantee marginal valuedurability10000NoteIf opposite cost is taken into consideration, at a present stage, it is not practical.* Guarantee marginal value : The number of times of a use limit which an offer company guarantees.
18 Preliminary Roadmap for Sockets A trend of SocketNeed to develop novel contactor such as zero-force architecture forultra high pin counts (narrow pitch) and high speed device testing.Surface mount type of stampingSurface mount of stamping contact pin with rubber componentPeripheralLeaf spring typeParticle inter-connect?Spring probe systemArea ArrayLeaf spring typeBarrel less type of spring probe pinOne side actuating type of spring probe pinFilm typeRubber typeMicro-spring?
19 Modeling and Simulation Difficulty of test development for design & Virtual tester tech.De fac’to program descriptionTest Board verification tech.Correct testCorrect test program?equipment?･Tester resource problems(timing,pattern length, etc.)･wrong wiring･ miss relay control point･ Ground noise･wrong parts･probe card (inductance)･reflection(missmatched Z)･Tester limitation(clump)･Wait time・Different testerDifficulttriangular・・・・・・・・・・Correct products?･imperfect circuit understanding･not fix test spec.･complex conditions of timingetc ････Virtual test operationVirtual tester technology
20 Modeling and Simulation Socket / ProbeTest boardMachine figure presentation,target electrical propertypresentationEquivalent length wiring,target transmissionimpedanceSmall boardSocketSocket/ProbeA large number are taken.Test boardBlock ringFormation of many pinsWorkability, SpeedConversion boardTest -BoardFormation of a special packageConversionOptimize wiring ,Adjust processingElectric circuit parameter extractionTester pinelectronics(Electro magnetic analysis)(Board analysis)Tester mother boardDRTesterxCPTest board verification technologyNew businessDUT-Tester transmissionThe necessity for a model1V3V25ΩＲSRL∽350mHＣＰ24mAＣＰ-24mAoutput SPICE and IBS modelDistributed Model, Tester Modetr=2.0ns/tf=2.4nstr=1.3ns/tf=1.8ns6Vtr=2.3ns/tf=12.8ns(Customer board design consideration)(Tester transmission way analysis technology)Device improvement in the speed,customer situation considerationIt is overly high-speed testing.(RAMBUS, cellular phone)High frequency Transition line considerationL/Ｒ ＣｉｒｃｕｉｔDiode Clamp CircuitI-LOAD CircuitOutput voltage, current regulationConcentration constantFig 2 T6672 Tester RingingCountermeasure Method(Voh,Vol,Ioh,Iol(Comparator capacity, driver impedance)DeviceTesterHigh-speed tester (125MHz) test mode waveform analysisSubject: socket / probe, a test board, and a testerEven if each shows information,the whole test board verification is difficult.
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