Presentation is loading. Please wait.

Presentation is loading. Please wait.

1 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Design and System Driver Chapters Spring Meeting April 2005.

Similar presentations


Presentation on theme: "1 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Design and System Driver Chapters Spring Meeting April 2005."— Presentation transcript:

1 1 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Design and System Driver Chapters Spring Meeting April 2005 Munich, Germany Design TWG (Europe, Asia, and U.S.) Albin, Arledge, Asada, Bernstein, Bertacco, Blaauw, Blanton, Brederlow, Briere, Carballo, Chen, Cohn, Cottrell, Darringer, Edwards, Furui, Gowda, Guardiani, Hiwatashi, Kahng, kashiwagi, Kawahira, Kozawa, Ishibashi, Kravets, Martin, McMillan, Nassif, Pan, Macd, Nukiyama, Pitchumani, Pixley, Rosenstiel, Read, Rodgers, Sakallah, Smith, Soma, Stok, Vertregt, Wilson, Yamamoto, Yamada, Yeh

2 2 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference 2005 Spring Deliverables 1. 10 new table drafts quantify design technology trends –Final version targeted by June 2. DFM preliminary model enables variability roadmap –DFM roadmapping tool + interface with other groups 3. Draft SoC cost model provides new type of driver –SoC model quantifies productivity and architecture trends

3 3 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Timeline DateMilestone April 12ITRS Europe meeting starts Current tables/roadmaps presented for review June 10DFM preliminary roadmap complete Revised tables/roadmaps completed NEMI roadmap mapping first version complete Draft Design and System Drivers due to editors July 11ITRS USA meeting starts Revised tables/roadmaps presented for review DFM roadmap presented for review NEMI mapping proposal for review Final Design Chapter due to editors Sep 19Finalized tables/roadmaps NEMI mapping, DFM roadmap finalized ITRS 2005 content frozen

4 4 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Design: Content organization Promotion of key design challenges –Small subset of them to top-level ORTC Design process System design Logic/circuit Physical D Design verification Design Test DFM (new) ProductivityPowerDFMInterferenceReliability General Selection Mapping

5 5 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Design: Content organization (II) Scope Complexity and Crosscutting Challenges Design Technology Challenges - Overall Challenges (5 challenges + table) - Design Methodology Trends (text) - System-level Design - Logical, Circuit, and Physical Design - AMS and RF-specific DT Trends and Challenges (revised) - Design Verification - Design Test

6 6 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Detailed Table Status SectionRequirementsSolutions SystemYes, draft Logic/ckt/physicalYes, draftYes, row definitions VerificationYes, draftYes, row definitions Design TestYes, draft DFMYes, draft Targeting 50-60 new rows –Leads: Rosenstiel, Soma, Bertacco, Kravets, Nassif/Kahng Next steps –Incorporate input until final version –Complete coloring

7 7 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference New Table: System-Level Requirements Year of Production20042007201020132016Driver Technology Nodehp90hp65hp45hp32hp22 % design block reuse3037434854SOC # available platforms2420151210SOC % available platforms supported by tools 110507090SOC % deviation of high level estimates (performance, area, power, costs) 5040302010SOC % SOC reconfigurability (SW and/or HW) 2028354250SOC % analog synthesizability (vs. digital) 1017243240SOC Source: Wolfgang Rosenstiels Team

8 8 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference New Table: System-Level Solutions Source: Wolfgang Rosenstiels Team Technology Node 20072008 2006 2005 2009201220152018 2010 201120132014 2016 2017 20192020 Research Required System-level component reuse Automated Interface Synthesis Explicit system-level energy- performance trade-off Multi-fabric implementation planning (AMS, RF, MEMS, …) SW-SW and SW-HW co-design and verification On-chip network design methods Chip-package co-design methods Development Pre-Production Improvement Time during which research, development, and qualification/pre-production should be taking place for solution. hp70hp50 hp18hp25hp35hp15 2021

9 9 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference RequirementMetric asynchronous global signaling#handshake-related components parameter uncertainty%-effect (on sign-off delay) simult. analysis objectives# of objectives during optimization MTTF contributionreliability factor circuit families# of circuit families in a design analog content synthesized% of a design design on predictable platformssuch as FPGAs (%) adaptive/self-repairing circuitsnumber of fuses per chip area unit leakageper device, probability distribution New Table: Logic/Ckt/Physical Requirements Source: Victor Kravetss Team

10 10 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference New Table: Logic/Ckt/Physical Requirements 20052007200920122014201620182020 commentshp90hp65hp45hp32 hp16 % of a design driven by handshake clocking 5%7%15%20% 30% 40% %-effect (on sign-off delay) 5%6%10%12%15%20% 25% # of objectives during optimization 4468888 reliability factor 11.21.41.822.22.52.7 # of circuit families in a single design (optimistic) 234 4 4 4 4 4 % of a design analog synthesized 10%15%17%30% 50% # times per device4 12 30600 Source: Victor Kravetss Team

11 11 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference New Table: Verification Requirements Verification requirements Bugs escape rate: bugs found after first tape out. bugs found after system integration until tape-out Code coverage percent of code coverage Functional coverage percent of the projects where it is used functional coverage goals for each thousand lines of HDL code correlation of size of functional coverage goal vs. escape rate Tape-out criteria examples: booting linux, total number of simulation cycle run, coverage.... Reuse ratio of fresh verification infrastructure vs. reused percent of reused infrastructure that is acquired from third parties Methodology effort spent in formal verification vs. simulation/emulation (in engineering days) effort spent in formal verification vs. simulation/emulation (in lines of HDL) Source: Valeria Bertaccos Team

12 12 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference New Table: DFT Requirements % components covered by DFT 1. DFT-support for test methodology of RX and TX circuit components for manufacturing defects and severe process variations. Note normal process variation and device mismatch should be comprehended in the analog design with compensation circuitry, which requires testing to assure its proper operation. % parallel / % separate 2. DFT-support for parallel or separate test of TX/RX for fault diagnosis. % control via TAP 3. Control of DFT features via JTAG or other industry-standard test access port. Standard availability 4. DFT / ATE interface standard. Need to develop to encourage open test architectures and solutions. DFT methodologies must work in conjunction with ATE to support a comprehensive test methodology. % re-use 5. Re-use of existing I/O circuit features to take measurements during test. Example: RX data clock recovery circuits can be re-used for a timing measurement. % accessible / % reconfigurable 6. Accessibility and reconfigurability of component-level DFT features for system-level validation / characterization (i.e. system link health) and system test. % hierarchical DFT 7. DFT-support for hierarchical system test and validation without descending to the component level. % reduction in functional test 8. DFT-support for on-die pattern generation and checking to reduce / avoid cost for functional test pattern development. % non-invasive test 9. DFT-support for non-invasive (non-intrusive) or minimally invasive (minimally intrusive) wafer level test. % low-speed / % high-speed DFT 10. DFT for both low-speed and at-speed test of digital / analog / mixed-signal / RF systems. %all-digital DFT 11. All-digital DFT for analog / mixed-signal / RF circuits and systems. DFT support for RF measurements (continuous method and / or modulated method). Availability 12. Variable-sensitivity DFT. Availability 13. DFT for DFY. % correlation 14. DFT output correlation to existing specification-based test methods. Quantization model and calculations 15. Quantization of DFT impact on system performance (noise, power, sensisitivity, bandwidth, etc.). % DFT support 16. DFT-support to test multiple-input multiple-output RF systems. Availability of FM (fault model) 17. Development of fault models / defect models appropriate for DFT-oriented test methods of digital / analog / mixed-signal / RF integrated systems. % DFT CAD tool available 18. CAD tools to support DFT incorporation into digital / analog / mixed-signal / RF systems Source: Mani SomasTeam

13 13 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference DFT Technology Requirements Near-termLong-term 2005200620072008200920102011201220132014201520162017201820192020 Technology node hp90hp65hp45hp32hp22hp16 % components covered by DFT 20 2530354045505560657075808590 % parallel / % separate 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 70.0 75.0 80.0 85.0 90.0 % control via TAP 25.0 30.0 35.0 40.0 45.0 50.0 60.0 70.0 75.0 80.0 90.0 100. 0 % re-use30 35 40 45 50 60 70 % accessible / % reconfigurable 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 70.0 75.0 80.0 85.0 90.0 % hierarchical DFT 20 2530354045505560657075808590 % reduction in functional test 20 2530354045505560657075808590 % non-invasive test 30354045505560657075808590 100 % low-speed / % high-speed DFT 20 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 70.0 75.0 80.0 85.0 90.0 %all-digital DFT30354045505560 808590 100 % correlation20 2530354045505560657075808590 % DFT support10 20 30 35 4045505560708090 Availability of FM (fault model) Analo g FM MS FM RF FM Syste m FM Impr ove % DFT CAD tool available 30354045505560657075808590 100

14 14 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference New Table: DFM Requirements Near-termLong-term year (2000-) 0505 060708091011121314151617181920 DFM hp90hp65hp45hp32hp22hp16 Mask cost ($m) 1.5 1.5 2.2 3 4.5 6 9 12 18 24 36 48 72 96 144 192 288 % Supply variability 1010 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? % CD variability 1010 10 ? 10 ? 10 ? % circuit performance variability3 33343536373839 40 % circuit power variability 3 55 56 57 58 59 60 61 62 Source: Carballo/Nassif/Pan/Kahng/Guardiani/Brederlow/Wong

15 15 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference New Table: DFM Solutions Detailed tables: DFM 20 05 20 06 20 07 20 08 20 09 20 10 20 11 20 12 20 13 20 14 20 15 20 16 20 17 20 18 20 1920 Technology node hp 90 hp 65 hp 45 hp 32 hp 22 hp 16 Tools that account for mask cost in their algorithms RET tools that are aware of circuit metrics (timing, power) Radically-restricted rules Statistical analysis and opt. tools and flows (Vdd, T, Vth) Statistical leakage analysis and optimization tools Architectures resistant to variability (redundancy, ECC) Adaptable and redundant circuits Post-tapeout RET interacting with synthesis, timing, P&R Source: Carballo/Nassif/Pan/Kahng/Guardiani/Brederlow/Wong

16 16 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference 2. SoC Cost Model Update, Inc. SW Mobile /Consumer SoC Memory PE-1 Peripherals PE-2PE-n … Main Prc. Design process System design Logic/circuit Physical D Design verification Design Test DFM (new) ProductivityPowerManufac.InterferenceReliability General Selection Updated productivity table cost Will preserve consistency

17 17 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference # of Processing Engines

18 18 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Processing Power Trends

19 19 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference HW Design Productivity Requirements

20 20 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference 3. New DFM Section –Outline INTRO DFM CHALLENGES -- NEAR TERM (>45 NM) –MASK COST –DATA EXPLOSION –LIMITATIONS OF LITHOGRAPHY HARDWARE RESOLUTION –VOLTAGE SUPPLY AND THRESHOLD VARIABILITY –BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY –HETEROGENEOUS COMPONENTS (AMS, MEMS, ERAM) –LEAKAGE AS A LIMITER OF MANUFACTURABILITY –VARIABILITY DFM CHALLENGES -- LONG TERM (<45 NM) -UNCONTROLLABLE CD AND DOPING VARIABILITY -EXTREME DEVICE AND CIRCUIT VARIABILITY -RET-awareness IN DESIGN -PACKAGE, SYSTEM, AND SW VARIABILITY -BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY – DESCRIPTION OF VARIABILITY MODEL

21 21 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference DFM Variability Framework NANA L eff W eff WLtt OX t ILD VtVt Intermediate parameters Gate delay (power)Wire delay (power) Performance (delay)Power (energy) R sheet (Vdd, T) Other TWGs (PIDS, Interconnect, etc.) Actual (bottom-up) / required (top-down) variability

22 22 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Roadmapping DFM Issues inc. Variability Current recommendation –Not to extend 10% CD control beyond 15% –Below 15% still unclear


Download ppt "1 DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Design and System Driver Chapters Spring Meeting April 2005."

Similar presentations


Ads by Google