1. EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. EE4271 VLSI Design

2. EE141 © Digital Integrated Circuits 2nd Wires 2 Modern Interconnect

3. EE141 © Digital Integrated Circuits 2nd Wires 3 Modern Interconnect - II

4. EE141 © Digital Integrated Circuits 2nd Wires 4 0.18 Source: Gordon Moore, Chairman Emeritus, Intel Corp. 0 50 100 150 200 250 300 Technology generation (  m ) Delay (psec) Transistor/Gate delay Interconnect delay 0.80.50.25 0.15 0.35 Interconnect Delay Dominates

5. EE141 © Digital Integrated Circuits 2nd Wires 5 Wire Model

6. EE141 © Digital Integrated Circuits 2nd Wires Capacitor  A capacitor is a device that can store an electric charge by applying a voltage  The capacitance is measured by the ratio of the charge stored to the applied voltage  Capacitance is measured in Farads

7. EE141 © Digital Integrated Circuits 2nd Wires 3D Parasitic Capacitance  Given a set of conductors, compute the capacitance between all pairs of conductors. - - - - - - - + + + + + C=Q/V 1V1V

8. EE141 © Digital Integrated Circuits 2nd Wires Simplified Model  Area capacitance (Parallel plate): area overlap between adjacent layers/substrate  Fringing/coupling capacitance:  between side-walls on the same layer  between side-wall and adjacent layers/substrate m2 m1 m3

9. EE141 © Digital Integrated Circuits 2nd Wires 9 The Parallel Plate Model (Area Capacitance) Capacitance is proportional to the overlap between the conductors and inversely proportional to their separation

10. EE141 © Digital Integrated Circuits 2nd Wires Wire Capacitance  More difficult due to multiple layers, different dielectric m2 m1 m3  =3.9  =8.0  =4.0  =4.1 multiple dielectric

11. EE141 © Digital Integrated Circuits 2nd Wires Simple Estimation Methods - I  C = Ca*(overlap area) +Cc*(length of parallel run) +Cf*(perimeter)  Coefficients Ca, Cc and Cf are given by the fab  Cadence Dracula  Fast but inaccurate

12. EE141 © Digital Integrated Circuits 2nd Wires Simple Estimation Methods - II  Consider interaction between layer i and layers i+1, i+2, i–1 and i–2  Cadence Silicon Ensemble  Accuracy  50%

13. EE141 © Digital Integrated Circuits 2nd Wires Library Based Methods  Build a library of tens of thousands of patterns and compute capacitance for each pattern  Partition layout into blocks, and match with the library  Accuracy  20%

14. EE141 © Digital Integrated Circuits 2nd Wires Accurate Methods In Industry  Finite difference/finite element method  Most accurate, slowest  Raphael  Boundary element method  FastCap, Hicap

15. EE141 © Digital Integrated Circuits 2nd Wires 15 Fringing versus Parallel Plate Fringing/Coupli ng capacitance dominates.

16. EE141 © Digital Integrated Circuits 2nd Wires Wire Resistance  Basic formula R=(  /h)(l/w)   : resistivity  h: thickness, fixed for a given technology and layer number  l: conductor length  w: conductor width h l w

17. EE141 © Digital Integrated Circuits 2nd Wires Sheet Resistance  Simply R=(  /h)(l/w)=R s (l/w)  R s : sheet resistance Ohms/square, where h is the metal thickness for that metal layer. Given a technology, h is fixed at each layer.  l: conductor length  w: conductor width l w

18. EE141 © Digital Integrated Circuits 2nd Wires Typical Rs (Ohm/sq) MinTypicalMax M1, M20.050.070.1 M3, M40.030.040.05 Poly152030 Diffusion1025100 N-well100020005000

19. EE141 © Digital Integrated Circuits 2nd Wires 19 Contact and Via  Contact:  link metal with diffusion (active)  Link metal with gate poly  Via:  Link wire with wire

20. EE141 © Digital Integrated Circuits 2nd Wires 20 Interconnect Delay

21. EE141 © Digital Integrated Circuits 2nd Wires Analysis of Simple RC Circuit state variable Input waveform ± v(t) C R v T (t) i(t)

22. EE141 © Digital Integrated Circuits 2nd Wires Analysis of Simple RC Circuit Step-input response: match initial state: output response for step-input: v0v0 v 0 u(t) v 0 (1-e -t/RC )u(t)

23. EE141 © Digital Integrated Circuits 2nd Wires 0.69RC  v(t) = v 0 (1 - e -t/RC ) -- waveform under step input v 0 u(t)  v(t)=0.5v 0  t = 0.69RC  i.e., delay = 0.69RC (50% delay) v(t)=0.1v 0  t = 0.1RC v(t)=0.9v 0  t = 2.3RC  i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd)  For simplicity, industry uses T D = RC (= Elmore delay)  We use both RC and 0.69RC in this course. In textbook, it always uses 0.69RC.

24. EE141 © Digital Integrated Circuits 2nd Wires Elmore Delay Delay 1.50%-50% point delay 2.Delay=RC (Precisely, 0.69RC)

25. EE141 © Digital Integrated Circuits 2nd Wires 25 Elmore Delay - III What is the delay of a wire?

26. EE141 © Digital Integrated Circuits 2nd Wires 26 Elmore Delay – IV Assume: Wire modeled by N equal-length segments For large values of N: Precisely, should be 0.69RC/2

27. EE141 © Digital Integrated Circuits 2nd Wires Elmore Delay - V 27 n1 n2 C/2 R n1 n2 R=unit wire resistance*length C=unit wire capacitance*length

28. EE141 © Digital Integrated Circuits 2nd Wires RC Tree Delay 28 27 2 2 1 1 3.5 Unit wire cap=1, unit wire res=1 4 2 7 4 2*(1+3.5+3.5+2+2)=24 24+7*3.5=48.5 24+4*2=32 RC Tree Delay=max{32,48.5}=48.5 Precisely, 0.69*48.5

29. EE141 © Digital Integrated Circuits 2nd Wires More Accurate RLC Delay Model 29 At time t=0, switch is on. This effect is not felt everywhere instantaneously. Rather, the effect is propagated with a speed u. Denote by c 0 the speed of light, epsilon the permittivity and mu the permeability of the dielectric of the medium which the wire is in, L and C the unit wire inductance and capacitance, respectively. According to Maxwell’s law, I=V/R at t=0 is not right since you assume that you can see R with 0 time

30. EE141 © Digital Integrated Circuits 2nd Wires RLC Delay - II 30 Voltage and Current at time t1 and t2 R0 is the resistance you can really see at t1. R cannot be seen yet.

31. EE141 © Digital Integrated Circuits 2nd Wires RLC Delay - III  What is R 0 ?  The front of the voltage travels from 0 to l. Suppose that the distance it moves is dx, the capacitance to be charged is Cdx. The charge is thus dQ=CdxV.  Current I=dQ/dt=CVdx/dt=CVu  where is called characteristic impedance.

32. EE141 © Digital Integrated Circuits 2nd Wires RLC Delay - IV  R 0 is a function of the medium  For Printed Circuit Board (PCB), it is about 50-75 ohm  For any x between 0 and l, we always have Ix=Vx/R 0,I l =V l /R 0 when x=l  Note that there is a resistor R. We should have I l =V l /R  What happens if R!= R 0 ?

33. EE141 © Digital Integrated Circuits 2nd Wires RLC Delay - V  At load, the wave will be reflected back to the source.  The amplitude and polarity of this reflected wave are such that the total voltage, the sum of incident voltage and reflected voltage, satisfies I l =V l /R  If the incident voltage is V, denote by pV the reflected voltage, where p is called the reflection coefficient.  If incident current is V/R 0, then reflected current is –pV/R 0  Thus, (V+pV)/(V/R 0 –pV/R 0 )=R.  p=(R/R 0 -1)/(R/R 0 +1)  R=R 0, p=0, no reflection  R=infty, p=1, wire is unterminated  R=0, p=-1, wire is short-circuited  There can be multiple rounds of reflections.

34. EE141 © Digital Integrated Circuits 2nd Wires RLC Delay Example  Consider a wire of length l, R 0 =100 ohm, R=900 ohm driven by the source resistance (transistor equivalent resistance) Rs= 14 ohm. Source voltage is 12V as a step input at time t=0. We want to compute the waveform at the end of l.  Reflection coefficient  At t=0, V1=12*R 0 /(R 0 +Rs)=10V since it cannot see R yet  At t=td=l/u, wave V1 arrives at the end and is reflected as V2=p R V1=8V. The total voltage at the end is V1+V2 =18V  At time t=2td, wave V2 arrives at the source and reflected as V3=p S V2=-0.75*8=-6V  At time t=3td, wave V3 arrives at the end and is reflected as V4=P R V3=-4.8V, so the total voltage at the end is V1+V2+V3+V4=7.2V  Continues this process. Next total voltage at the end is 13.7V.  The total voltage at l will converge to 12*R/(R+Rs)=11.7V Rs=14

35. EE141 © Digital Integrated Circuits 2nd Wires RLC Delay Example - II 35 Voltage at the end of l

36. EE141 © Digital Integrated Circuits 2nd Wires When To Use RLC Model  The voltages at first few td have large magnitudes and are quite different from RC model. This is because Rs<R 0.  When Rs>>R 0, V1 is small and is the reflected voltage V2.  The total voltage at the end of the wire will gradually increase to 11.7V, which is the same as predicted by RC model.  Thus, RLC model should only be used when Rs is small (see also Figure 4-21 in the textbook) since RLC model is expensive to compute.  RLC model can be used when the switching is fast enough since signal transition time is proportional to Rs. v0v0 v 0 u(t) v 0 (1-e -t/RC )u(t) RC Model, V0=12

37. EE141 © Digital Integrated Circuits 2nd Wires Summary  Wire capacitance  Fringing/coupling capacitance dominates area capacitance  Wire resistance  RC Elmore delay model for wire  For single wire, 0.69RC/2  RC tree  RLC model for wire  Reflection  When to use