1. Evolution in Complexity Evolution in Transistor Count

2. Evolution in Speed/Performance

3. Intel 4004 Micro- Processor Intel Pentium (II) microprocessor

4. Design Abstraction Levels

5. Silicon in 2010 Die Area:2.5x2.5 cm Voltage:0.6 V Technology:0.07  m

6. Jan M. Rabaey The Devices

7. The MOS Transistor

8. Current-Voltage Relations

9. Dynamic Behavior of MOS Transistor

10. THE INVERTERS

11. DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance –Speed (delay) –Power Consumption –Energy

12. The CMOS Inverter: A First Glance

13. VTC of Real Inverter

14. Delay Definitions

15. CMOS Inverters Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2  m =2

16. Scaling Relationships for Long Channel Devices

17. COMBINATIONAL LOGIC

18. Overview

19. Static CMOS

20. Example Gate: NAND

21. Transistor Sizing

22. 4-input NAND Gate In1In2In3In4 Vdd GND Out

23. Ratioed Logic

24. Pseudo-NMOS

25. Dynamic Logic

26. Example

27. Cascading Dynamic Gates

28. Domino Logic

29. Where Does Power Go in CMOS?

30. SEQUENTIAL LOGIC

31. Master-Slave Flip-Flop

32. CMOS Clocked SR- FlipFlop

33. 2 phase non-overlapping clocks

34. Pipelining

35. Arithmetic Building Blocks

36. A Generic Digital Processor

37. Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath ( adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

38. Bit-Sliced Design

39. Layout Strategies for Bit-Sliced Datapaths

40. Layout of Bit-sliced Datapaths

41. COPING WITH INTERCONNECT

42. Impact of Interconnect Parasitics

43. Using Cascaded Buffers

44. ISSUES IN TIMING

45. The Ellmore Delay

46. The Clock Skew Problem