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I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.

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Presentation on theme: "I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011."— Presentation transcript:

1 I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011

2 Three Key Pillars of EDA360 © 2011 Cadence Design Systems, Inc. All Rights Reserved. 2 System Realization SoC Realization Silicon Realization EDA360

3 Three Key Pillars of EDA360 © 2011 Cadence Design Systems, Inc. All Rights Reserved. 3 EDA360 System Realization SoC Realization Silicon Realization

4 Three Key Pillars of EDA360 © 2011 Cadence Design Systems, Inc. All Rights Reserved. 4 EDA360 System Realization SoC Realization Silicon Realization Traditional EDA, including all the required technologies to design, verify, and implement silicon, packages, and boards

5 Three Key Pillars of EDA360 © 2011 Cadence Design Systems, Inc. All Rights Reserved. 5 EDA360 System Realization SoC Realization Silicon Realization Software content (IP), tools, and services that enable the delivery, integration, and support of high-quality IP required in complex SoCs Traditional EDA, including all the required technologies to design, verify, and implement silicon, packages, and boards

6 Three Key Pillars of EDA360 © 2011 Cadence Design Systems, Inc. All Rights Reserved. 6 EDA360 System Realization SoC Realization Silicon Realization Software content (IP), tools, and services that enable hardware-aware system development and verification Software content (IP), tools, and services that enable the delivery, integration, and support of high-quality IP required in complex SoCs Traditional EDA, including all the required technologies to design, verify, and implement silicon, packages, and boards

7 Silicon Realization – Customer Challenges Time to market –Disaggregated, global design chain limits visibility and predictability for complex designs – causing schedule delays and respins –Lack of true holistic and integrated silicon-package-board flows causes productivity gap –Reuse Profitability –Design failure catastrophic –Functionality, performance, and power improvements contribute to higher margins –Manufacturability © 2011 Cadence Design Systems, Inc. All Rights Reserved. 7

8 System Realization – Customer Challenges Software development trails hardware development, impacting time-to-market Hardware-software integration complexity impeding product shipments, quality Effective and predictable system and sub-system verification © 2011 Cadence Design Systems, Inc. All Rights Reserved. 8

9 System Realization – Market Landscape Development costs rising © 2011 Cadence Design Systems, Inc. All Rights Reserved. 9 Millions Software HW Implementation and Manufacturing HW Design and Verification Source: IBS 2009

10 System Realization – Market Landscape Market window shrinking; growing penalties for delay © 2011 Cadence Design Systems, Inc. All Rights Reserved. 10 Source: IBS Percent Revenue Loss

11 Application Application Framework / GUI Libraries O/S O/S Runtimes System Sample Challenges at Each Realization Layer SoC Silicon Test Programs Mixed SignalLow PowerAdvanced Node Giga-Gates/GHz DFM Verification IP Configuration Drivers Power Management … Scheduler Hardware System Architecture

12 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 12 Common Design Database

13 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 13 Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

14 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 14 Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools)

15 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 15 Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

16 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 16 Silicon Realization Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

17 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 17 Silicon Realization Chip (Spec to GDSII) Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

18 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 18 Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

19 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 19 Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Mixed-Signal Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

20 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 20 Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Mixed-Signal Flow RF Sub Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

21 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 21 Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow RF Sub Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

22 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 22 Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

23 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 23 Silicon Realization Chip (Spec to GDSII)Package Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

24 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 24 Silicon Realization Chip (Spec to GDSII)Package Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

25 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 25 Silicon Realization Chip (Spec to GDSII)Package Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

26 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 26 Silicon Realization Chip (Spec to GDSII)Package Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

27 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 27 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

28 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 28 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

29 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 29 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

30 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 30 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation Signal and Power Integrity Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

31 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 31 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

32 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 32 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

33 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 33 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Design IP Synthesizable (Soft) Process-Specific (Hard) Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

34 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 34 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Design IP Verification IP Synthesizable (Soft) Process-Specific (Hard) Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

35 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 35 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Design IP Verification IP IP-Centric Design Environment Synthesizable (Soft) Process-Specific (Hard) Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

36 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 36 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Design IP Verification IP IP-Centric Design Environment Synthesizable (Soft) Process-Specific (Hard) System Realization Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

37 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 37 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Design IP Verification IP IP-Centric Design Environment Synthesizable (Soft) Process-Specific (Hard) System Realization MiddlewareOSDrivers Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way) Apps

38 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 38 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Design IP Verification IP IP-Centric Design Environment Synthesizable (Soft) Process-Specific (Hard) System Realization Hardware-Aware Software Development Environment Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way) MiddlewareOSDriversApps

39 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 39 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Design IP Verification IP IP-Centric Design Environment Synthesizable (Soft) Process-Specific (Hard) System Realization Hardware-Aware Software Development Environment System-Level Hardware Design Environment Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way) MiddlewareOSDriversApps

40 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 40 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Design IP Verification IP IP-Centric Design Environment Synthesizable (Soft) Process-Specific (Hard) System Realization Hardware-Aware Software Development Environment System-Level Hardware Design Environment Virtual Prototyping Environment System-Level Simulation System-Level Emulation Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way) MiddlewareOSDriversApps

41 EDA360 – The Technical Version © 2011 Cadence Design Systems, Inc. All Rights Reserved. 41 Silicon Realization Chip (Spec to GDSII)PackageBoard Digital Flow (GigaGates/GHz) Mixed-Signal Flow Custom/Analog Flow Low-Power Flow RF Sub Flow Single Chip Multi Chip 2.5D And 3D Layout and Routing AMS Simulation FPGA and PCB Codesign Signal and Power Integrity Silicon Realization High-Quality IP Design IP Verification IP IP-Centric Design Environment Synthesizable (Soft) Process-Specific (Hard) System Realization Hardware-Aware Software Development Environment System-Level Hardware Design Environment Virtual Prototyping Environment System-Level Simulation System-Level Emulation System-Level Verification Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way) MiddlewareOSDriversApps

42 EDA360 Case Study: Agilent InfiniiVision Digital/Mixed-Signal Sampling Oscilloscope © 2011 Cadence Design Systems, Inc. All Rights Reserved. 42 Reproduced with Permission, Courtesy of Agilent Technologies, Inc. Note: This case study is based on public, published data and nothing is implied about the EDA tools used to develop this product.

43 Agilent InfiniiVision 2000/3000 DSO/MSO System Block Diagram © 2011 Cadence Design Systems, Inc. All Rights Reserved. 43 Measurement Buffer (64K) Acquisition Memory Manager DRAM ADC Data Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Trigger Display Plotter DRAM GUI Controller Mask Waveform Synthesis A/D Converter Measurement and Search Acceleration* User Interface Host Processor LCD Panel Analog Signals Digital Signals Diagram as published in EE Times * 23 automated measurements such as voltage, time, and frequency as well as four waveform math functions including FFT

44 Agilent InfiniiVision 2000/3000 DSO/MSO System Intent © 2011 Cadence Design Systems, Inc. All Rights Reserved. 44 Measurement Buffer (64K) Acquisition Memory Manager DRAM ADC Data Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Trigger Display Plotter DRAM GUI Controller Mask Waveform Synthesis A/D Converter Measurement and Search Acceleration User Interface Host Processor LCD Panel Analog Signals Digital Signals 2 Gbytes/sec 4 Gbytes/sec Diagram as published in EE Times

45 Agilent InfiniiVision 2000/3000 DSO/MSO System Intent © 2011 Cadence Design Systems, Inc. All Rights Reserved. 45 Measurement Buffer (64K) Acquisition Memory Manager DRAM ADC Data Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Trigger Display Plotter DRAM GUI Controller Mask Waveform Synthesis A/D Converter Measurement and Search Acceleration User Interface Host Processor LCD Panel Analog Signals Digital Signals 2 Gbytes/sec 4 Gbytes/sec >4 Gbytes/sec Diagram as published in EE Times

46 Agilent InfiniiVision 2000/3000 DSO/MSO System Intent © 2011 Cadence Design Systems, Inc. All Rights Reserved. 46 Measurement Buffer (64K) Acquisition Memory Manager DRAM ADC Data Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Trigger Display Plotter DRAM GUI Controller Mask Waveform Synthesis A/D Converter Measurement and Search Acceleration User Interface Host Processor LCD Panel Analog Signals Digital Signals 2 Gbytes/sec 4 Gbytes/sec >4 Gbytes/sec >>4 Gbytes/sec Diagram as published in EE Times

47 Agilent InfiniiVision 2000/3000 DSO/MSO System Partitioning © 2011 Cadence Design Systems, Inc. All Rights Reserved. 47 Measurement Buffer (64K) Acquisition Memory Manager DRAM ADC Data Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Trigger Display Plotter DRAM GUI Controller Mask Waveform Synthesis A/D Converter Measurement and Search Acceleration Processor running Win CE LCD Panel Analog Signals Digital Signals MegaZoom IV SoC Diagram as published in EE Times

48 Agilent InfiniiVision 2000/3000 DSO/MSO System Partitioning © 2011 Cadence Design Systems, Inc. All Rights Reserved. 48 Measurement Buffer (64K) Acquisition Memory Manager DRAM ADC Data Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Trigger Display Plotter DRAM GUI Controller Mask Waveform Synthesis A/D Converter Measurement and Search Acceleration Processor running Win CE LCD Panel Analog Signals Digital Signals MegaZoom IV SoC On-Chip DRAM allows High- Bandwidth Connections On-chip DRAM allows wide, high-bandwidth connections Diagram as published in EE Times

49 Agilent MegaZoom IV SoC © 2011 Cadence Design Systems, Inc. All Rights Reserved. 49 Reproduced with Permission, Courtesy of Agilent Technologies, Inc.

50 Agilent InfiniiVision 2000 X-Series DSO Circuit Board © 2011 Cadence Design Systems, Inc. All Rights Reserved. 50 Image courtesy of David Jones, www.eevblog.com

51 Agilent InfiniiVision 2000 X-Series DSO Circuit Board © 2011 Cadence Design Systems, Inc. All Rights Reserved. 51 Image courtesy of David Jones, www.eevblog.com

52 Detail: Board-Level Design Intent © 2011 Cadence Design Systems, Inc. All Rights Reserved. 52 Serpentines ensure that all analog inputs reach the ADC simultaneously Differential-pair serpentines ensure that all analog inputs reach the ADC simultaneously Image courtesy of David Jones, www.eevblog.com

53 Agilent InfiniiVision 2000 X-Series DSO Circuit Board © 2011 Cadence Design Systems, Inc. All Rights Reserved. 53 Quad 8-bit, 1-Gsample/sec ADC MegaZoom IV SOC FPGA ST Micro SPEAr600 MPU with two ARM9 processor cores Image courtesy of David Jones, www.eevblog.com

54 ST Microelectronics SPEAr600 Block Diagram © 2011 Cadence Design Systems, Inc. All Rights Reserved. 54 FPGA Interface

55 Why use an ST Micro SPEAr600? © 2011 Cadence Design Systems, Inc. All Rights Reserved. 55 Less than $9 in production volumes! Win CE Support FPGA Interface

56 Three Key Pillars of EDA360 © 2011 Cadence Design Systems, Inc. All Rights Reserved. 56 System Realization SoC Realization Silicon Realization EDA360

57 © 2011 Cadence Design Systems, Inc. All rights reserved. 57 Questions and Answers

58

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