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Department of Computer Engineering Tallinn University of Technology Estonia Final Workshop of CDC 2002-2007 Tallinn, Brotherhood of the Blackheads, 21.

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Presentation on theme: "Department of Computer Engineering Tallinn University of Technology Estonia Final Workshop of CDC 2002-2007 Tallinn, Brotherhood of the Blackheads, 21."— Presentation transcript:

1 Department of Computer Engineering Tallinn University of Technology Estonia Final Workshop of CDC 2002-2007 Tallinn, Brotherhood of the Blackheads, 21 – 22 January 2008 A multi-layer research and training platform for system-on-chip testing: Hardware, Software and Web Interface Artur Jutman Dept. of Computer Engineering Tallinn University of Technology Estonia

2 A multi-layer research and training platform for system-on-chip testing 2 Outline Introduction and motivation Different layers of the platform HW tools PC-based tools Web interface E-Learning tools Conclusions and discussion

3 A multi-layer research and training platform for system-on-chip testing 3 Motivation Cutting Edge Research − Needs custom developed algorithms and/or tools PhD Students − Need to run their experiments Undergraduate Students − Need introduction to the topic Department − Needs training materials and research

4 A multi-layer research and training platform for system-on-chip testing 4 Different layers of the platform Web Tools PC Tools Hardware Tools

5 A multi-layer research and training platform for system-on-chip testing 5 Main components of the platform DefSim - an integrated measurement environment for physical defect study in CMOS circuits. TurboTester – a research and training toolkit with extensive set of tools for digital test and design for testability Web-based runtime interface for remote access to our tools Java applets – illustrative e-learning software written specifically for the web Other tools

6 A multi-layer research and training platform for system-on-chip testing 6 Different layers of the platform Web Tools PC Tools Hardware Tools

7 A multi-layer research and training platform for system-on-chip testing 7 Defect Study using DefSim DefSim is an integrated circuit (ASIC) and a measurement equipmrnt for experimental study of CMOS defects. The central element of the DefSim equipment is an educational IC with a large variety of shorts and opens physically inserted into a set of simple digital circuits. The IC is attached to a dedicated measurement box serving as an interface to the computer. The box supports two measurement modes - voltage and I DDQ testing. http://www.defsim.com

8 A multi-layer research and training platform for system-on-chip testing 8 − Standard industrial CMOS technology − Area 19.90 mm 2 − Approx. 48000 transistors − 62 pins − JLCC68 package A built-in current monitor for I DDQ testing is implemented in each block. DefSim IC details

9 A multi-layer research and training platform for system-on-chip testing 9 NAND2 cell with floating gate VDD GND Q A B X Implementation of defects

10 A multi-layer research and training platform for system-on-chip testing 10 VDD GND Q A B NAND2 cell with D-S short (missing poly) Altogether there are over 500 different defects on the chip Implemented defects are shorts and opens in metal and poly layers To be close to the silicon reality each cell is loaded and driven by standard non-inverting buffers Implementation of defects

11 A multi-layer research and training platform for system-on-chip testing 11 DefSim in the classroom With DefSim you can Observe the truth table of correct circuit Observe the truth table of defective circuit Obtain defect/fault tables for all specific defects Define test patterns automatically or manually Activate IDDQ and voltage measurements Study behavior of bridging and open faults Study and compare different fault models

12 A multi-layer research and training platform for system-on-chip testing 12 “Plug and Play” – dedicated hardware and software DefSim lab environment

13 A multi-layer research and training platform for system-on-chip testing 13 Different layers of the platform Web Tools PC Tools Hardware Tools

14 A multi-layer research and training platform for system-on-chip testing 14 Used in 100+ institutions in 40+ countries Design Error Diagnosis Test Generators BIST Emulator Design Test Set Levels: Gate Macro RTL Fault Table Test Set Optimizer Methods: BILBO CSTP Hybrid Faulty Area Circuits: Combinational Sequential Logic Simulator Formats: EDIF AGM Defect Library Hazard Analysis Data Specifi- cation Algorithms: Deterministic Random Genetic Multivalued Simulator Fault models: Stuck-at faults Physical defects Fault Simulator http://www.pld.ttu.ee/tt PC-Based Toolkit – Turbo Tester

15 A multi-layer research and training platform for system-on-chip testing 15 Freeware Freeware Downloadable via the Web Downloadable via the Web Windows, Linux, UNIX/Solaris Windows, Linux, UNIX/Solaris EDIF design interface EDIF design interface ATPGs, BIST, simulators, test compaction ATPGs, BIST, simulators, test compaction Provides homogeneous environment for research and training Provides homogeneous environment for research and training Turbo Tester: Basic Facts

16 A multi-layer research and training platform for system-on-chip testing 16 Different layers of the platform Web Tools PC Tools Hardware Tools

17 A multi-layer research and training platform for system-on-chip testing 17 BIST Analyzer: covered topics Test Pattern Generators (PRPG): − LFSR − Modular LFSR − Cellular Automata − GLFSR − Weighted TPG − etc. Combined Techniques (PRPG + Memory): − Reseeding − Multiple polynomial BIST − Hybrid BIST − Bit-Flipping BIST − Column matching BIST − etc. BIST Control Unit Circuit Under Test (CUT) Test Pattern Generator (PRPG)........ Output Response Analyzer (MISR) BIST Memory Typical BIST Architecture

18 A multi-layer research and training platform for system-on-chip testing 18 Embedded generators (PRPG) and their properties PRPG optimization methodologies and algorithms Combined BIST solutions (PRPG+memory) Fault detection and diagnosis in BIST BIST Analyzer: covered topics

19 A multi-layer research and training platform for system-on-chip testing 19 BIST Analyzer

20 A multi-layer research and training platform for system-on-chip testing 20 Different layers of the platform Web Tools PC Tools Hardware Tools

21 A multi-layer research and training platform for system-on-chip testing 21 Web Interface

22 A multi-layer research and training platform for system-on-chip testing 22 Different layers of the platform Web Tools PC Tools Hardware Tools

23 A multi-layer research and training platform for system-on-chip testing 23 E-Learning software on DFT http://www.pld.ttu.ee/applets

24 A multi-layer research and training platform for system-on-chip testing 24 Essential supplement to the university lectures Accessibility over Internet Visual content Comprehensive examples Better organization of teaching materials Based on free educational software Distance learning & computer aided teaching Easy to implement in other universities Constantly updated Benefits of e-learning software

25 A multi-layer research and training platform for system-on-chip testing 25 Test Generation Error Diagnosis Built-In Self-Test Design for Testability Test and Diagnostics RTL Design and Test Boundary Scan Applet on Basics of Test & Diagnostics Applet on RTL Design and Test Applet on Boundary Scan Standard Schematic & DD Editor Turbo Tester Group of Applets on Control Part Decomposition E-Learning Software Java Applets Turbo Tester Scenario 4 Design for Testability Scenario 3 Built-InSelf-Test Scenario 2 ErrorDiagnosis Scenario 1 TestGeneration Scenario 4 Design for Testability Scenario 3 Built-InSelf-Test Scenario 2 ErrorDiagnosis Scenario 1 TestGeneration Supporting Materials Learning Scenarios Web based tools for classroom, home and exams Tools for laboratory research

26 A multi-layer research and training platform for system-on-chip testing 26 E-Learning Software Logic level diagnostics System level test & DfT Software for classroom, home, labs and exams: http://www.pld.ttu.ee/applets Boundary Scan

27 A multi-layer research and training platform for system-on-chip testing 27 manual test pattern generation assisted by the applet generation of pseudo-random test vectors by LFSR fault simulation & study of fault table combinational fault diagnosis using fault tables sequential fault diagnosis by guided probing Applet on basics of test

28 A multi-layer research and training platform for system-on-chip testing 28 design of a data path and control path (microprogram) on RT level investigation of tradeoffs between speed of the system & HW cost RT-level simulation and validation gate-level deterministic test generation and functional testing fault simulation logic and circular BIST, functional BIST, etc. design for testability Applet on RT-level design and test

29 A multi-layer research and training platform for system-on-chip testing 29 Simulation of operation of TAP ControllerSimulation of operation of TAP Controller Illustration of work of BS registersIllustration of work of BS registers Insertion and diagnosis of interconnection faultsInsertion and diagnosis of interconnection faults Design/editing of BS structures using the BSDL languageDesign/editing of BS structures using the BSDL language Design/description of the target board using several chipsDesign/description of the target board using several chips Applet on Boundary Scan

30 A multi-layer research and training platform for system-on-chip testing 30 An applet targeted at binding all the applets and the Turbo Tester Supportedinterface formats are: AGMDWGVHDLGIFEDIF?PostScript? Design for Testability Applet on Basics of Test & Diagnostics Applet on RTL Design and Test Applet on Boundary Scan Standard Schematic & DD Editor AGM, DWG AGM, GIF AGM AGM,GIF Main functions of the applet are: gate-level schematic editor gate-level schematic editor SSBDD editor SSBDD editor schematic ↔ SSBDD on-the-fly schematic ↔ SSBDD on-the-fly converter converter different format reader/converter different format reader/converter Schematic and DD editor

31 A multi-layer research and training platform for system-on-chip testing 31 Design Specification Design Implementation Test Vector File Verification Results XTimport Tool ATPG Circuit Schematic Human Being Diagnostic Vectors Report File Prediag Tool Verification Tool Circuit Netlist Intermediate Diagnosis Vecmanager Tool Final Diagnosis Turbo Tester tools and formats Other Example of a lab work scenario

32 A multi-layer research and training platform for system-on-chip testing 32 Conclusions & Discussion The main features of the platform: Research engine + training software Layered structure HW and SW components Remote access Distance learning and e-learning Computer-aided teaching Freeware

33 A multi-layer research and training platform for system-on-chip testing 33 Our Tools on the Web The Turbo Tester home page http://www.pld.ttu.ee/tt/ The Turbo Tester web-server page http://www.pld.ttu.ee/webtt/ DefSim home page http://www.defsim.com Java applets home page http://www.pld.ttu.ee/applets/

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