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1 Flutuação de Dopantes Efeitos Quánticos Problemas Variação do V TH Intersubband scattering.

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Presentation on theme: "1 Flutuação de Dopantes Efeitos Quánticos Problemas Variação do V TH Intersubband scattering."— Presentation transcript:

1 1 Flutuação de Dopantes Efeitos Quánticos Problemas Variação do V TH Intersubband scattering

2 2 Electron concentration (Poisson)Electron concentration (Poisson+Schrödinger ) W si t si W si =t si =20 nm / MS =0V / V G = 0.0V / V G2 =0V / N a =5x10 17 cm -3 / T=300K

3 3 W si =t si =20 nm / MS =0V / V G = 1.5V / V G2 =0V / N a =5x10 17 cm -3 / T=300K W si t si Electron concentration (Poisson)Electron concentration (Poisson+Schrödinger )

4 4 Electron concentration (Poisson) Electron concentration (Poisson+Schrödinger ) W si t si W si =t si = 5 nm / MS =0V / V G =0.0V / V G2 =0V / N a =5x10 17 cm -3 / T=300K

5 5 Electron concentration (Poisson)Electron concentration (Poisson+Schrödinger ) W si =t si = 5 nm / MS =0V / V G =1.5V / V G2 =0V / N a =5x10 17 cm -3 / T=300K W si t si

6 6 2D Simulation (Quantum) Electron concentration

7 7 Flutuação de Dopantes Efeitos Quánticos Problemas Variação do V TH Intersubband scattering

8 8 First (lowest) subband energy level and Threshold voltage "Quantum-Mechanical Effects in Trigate SOI MOSFETs", J.P. Colinge, J. C. Alderman, W. Xiong, and C. R. Cleavelin, IEEE Transactions on Electron Devices, Vol. 53, no 5, pp. 1131-1136, 2006

9 9 Corrente de Dreno Poisson equation only (P) or Poisson+Schrödinger solver (P+S) "Quantum-Mechanical Effects in Trigate SOI MOSFETs", J.P. Colinge, J. C. Alderman, W. Xiong, and C. R. Cleavelin, IEEE Transactions on Electron Devices, Vol. 53, no 5, pp. 1131-1136, 2006

10 10 Flutuação de Dopantes Efeitos Quánticos Problemas Variação do V TH Intersubband scattering

11 11 Inter-Subband Scattering (2D GaAs) Inter-Subband Scattering (2D GaAs)

12 12 Efeitos Quánticos: Inter-subband scattering At low temperature

13 13 At room temperature ! Efeitos Quánticos: Inter-subband scattering

14 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium 150nm Buried oxide 65 nm top silicon layer thickness (H FIN ) gate dielectric = 2.3 nm HfSiON on 1 nm SiO 2 midgap metal gate: 5 nm TiN layer + 100nm thick polysilicon capping 1 x10 15 cm -3 channel concentration Experimental Results FinFET/Tri-Gate Technology

15 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium USP - University of Sao Paulo 15 *T. Poiroux et al., Microelectronics Engineering, 80, 378 (2005). For MuGFETs Devices (*): Threshold Voltage - MuGFET The influence of side gates are considerably higher than the top gate for W fin = 20 nm (almost double gate) Top gate Side gate

16 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium USP - University of Sao Paulo 16 *T. Poiroux et al., Microelectronics Engineering, 80, 378 (2005). For MuGFETs Devices (*): Threshold Voltage - MuGFET Workfunction difference Between the gate and silicon film

17 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium USP - University of Sao Paulo 17 For MuGFETs Devices: Threshold Voltage - MuGFET Potential in the channel

18 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium USP - University of Sao Paulo 18 Confinement induced by the quantum well W FIN = 20 nm For MuGFETs Devices: Threshold Voltage - MuGFET *T. Poiroux et al., Microelectronics Engineering, 80, 378 (2005). variation of the minimum energy in the conduction band

19 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium USP - University of Sao Paulo 19 Confinement induced by the quantum well W FIN = 20 nm Therefore the last term can be neglected due to the W fin used in this study has 20 nm For MuGFETs Devices: Threshold Voltage - MuGFET

20 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium When W Fin decreases Better control of the back channel by side walls gm ramp disappears W Fin V th [6] T. Poiroux et al., Micr. Eng., vol. 80, p. 378, 2005. gm max reduction is due to the electron mobility degradation in sidewall (110) crystal orientation with respect to the (100) plane W Fin Sidewalls conduction

21 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium Triple-Gate nFET Strain Technology V th g m,max Strain

22 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium Devices Characteristics – TiN Thickness Study Metal Gate - TiN IMEC/Belgium: Gate dielectric : 1 nm SiO 2 chemical oxide 2.3 nm MOCVD HfSiO t oxb = 150nm H fin = 65nm N a = 1x10 15 cm -3 Metal Gate – TiN 2nm (64 ALD cycles) 5nm (160 ALD cycles) 10nm (320 ALD cycles) n type MuGFETs 10 fins W fin = 2, 1, 0.5, 0.2, 0.17 m W fin,eff = W fin - 0.13mm L = 10 m *I. Ferain et al., ESSDERC, p. 202-205, 2008.

23 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium TiN Thickness Influence on gm Thinner TiN reduces slightly the onset of GIFBE IGIG Back interface accumulated (Fully depleted) to see GIFBE V T increases V T decreases Thinner TiN metal gate V FB eWF *Rodrigues M, Martino JA, Collaert N, Mercha A, Simoen E, Claeys C (2009)EuroSOI 2009

24 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium Devices Characteristics – Gate Stack n type MuGFETs W fin = 2 m 10 fins L = 10 m t oxb = 145nm H fin = 65nm Na = 1x10 15 cm -3 REF(1) (2) (3) (4) (5) 1 nm RTO (IL) 2.3nm HfSiO PE-ALD TiN Poly-Si TiN HfSiO SiO 2 5nm Dy 2 O 3 Cap Layer HfSiO SiO 2 HfSiO SiO 2 2nm 3nm Poly-Si 1 nm Poly-Si HfSiO SiO 2 Poly-Si HfSiO SiO 2 4 nm 1 nm Poly-Si HfSiO SiO 2 Poly-Si HfSiO SiO 2 1 nm 4 nm 0.5 nm Poly-Si HfSiO SiO 2 5 nm 0.5 nm IMEC/Belgium: *VLSI Symp. Dig. Techn. Papers, p. 14 (2008)- IMEC process

25 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium Gate Stack Influence on gm (*) *Martino JA, et al (2009), SOI Symposium, ECS Transactions. V T (eWF) GIFBE (higher V GF ) ( I G )

26 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium FinFET/Tri-Gate Technology (High N A ) (*) *Andrade MGC, Martino JA (2008), Solid-State Electronics, 52, 1877–1883.

27 USP - University of Sao Paulo University of Sao Paulo, Brazil - Imec, Belgium Higher N A - three peaks are observed. V T,TC : Top Corners V T,BC : Bottom Corners V T,SG V T,TG :Sidewall and Top surfaces at the same time FinFET/Tri-Gate Technology (High N A )

28 28 Uso de isolantes de porta com alta constante dielétrica e/ou uso de Múltiplas Portas (FinFET) Incrementar a corrente (Silício tensionado, SiGe, Ge, Múltiplas Portas (FinFET)). Modificar a estrutura do MOSFET para melhorar o acoplamento eletrostático: MOS conv. SOI Múltiplas Portas (FinFET) Para seguir a Lei de Moore é necessário: CONCLUSÕES

29 29 Jean-Pierre Colinge Alunos de Mestrado e Doutorado da EPUSP. Colegas Professores e Doutores da USP, FEI e UNICAMP. FAPESP: Projeto Temático CNPq – INCT-NAMITEC : Prof. Jacobus Swart Agradecimentos


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